MC100ES6111FAR2 IDT, Integrated Device Technology Inc, MC100ES6111FAR2 Datasheet - Page 7

• Manufacturer Part Number: MC100ES6111FAR2
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of MC100ES6111FAR2

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 2700MHz
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: LQFP
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 32
• Quiescent Current: 100mA
• Lead Free Status / RoHS Status: Not Compliant

MPC100ES6111 Data Sheet
Understanding the Junction Temperature Range of the
MC100ES6111
capabilities of the MC100ES6111, the MC100ES6111 is specified,
characterized and tested for the junction temperature range of T
0°C to +110°C. Because the exact thermal performance depends on
the PCB type, design, thermal management and natural or forced air
convection, the junction temperature provides an exact way to
correlate the application specific conditions to the published
performance data of this data sheet. The correlation of the junction
temperature range to the application ambient temperature range
and vice versa can be done by calculation:
(2s2p board, 200 ft/min airflow, see
consumption of 610 mW (all outputs terminated 50 ohms to V
V
MC100ES6111 is approximately T
ambient temperature in this example case calculates to –33°C (the
maximum ambient temperature is 77°C, see
the minimum junction temperature specification of the
MC100ES6111 does not have a significant impact on the device
functionality. However, the continuous use of the MC100ES6111 at
high ambient temperatures requires thermal management to not
exceed the specified maximum junction temperature. Please see
the Freescale application note AN1545 for a power consumption
calculation guideline.
MPC100ES6111 REVISION 6 OCTOBER 1, 2009
CC
To make the optimum use of high clock frequency and low skew
Assuming a thermal resistance (junction to ambient) of 54.4°C/W
Table 8 . Ambient Temperature Range (P
= 3.3 V, frequency independent), the junction temperature of the
1. The MC100ES6111 device function is guaranteed from
Natural convection
T
A
100 ft/min
200 ft/min
400 ft/min
800 ft/min
= –40°C to T
R
thja
(2s2p board)
J
= 110°C
T
J
= T
59.0°C/W
54.4°C/W
52.5°C/W
50.4°C/W
47.8°C/W
A
+ R
A
thja
+ 33°C, and the minimum
Table
⋅ P
T
tot
4) and a typical power
A
–36°C
–33°C
–32°C
–30°C
–29°C
, Min
Table
tot
(1)
= 610 mW)
8). Exceeding
APPLICATIONS INFORMATION
T
A
74°C
77°C
78°C
79°C
81°C
, Max
TT
,
J
=
7
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER
Maintaining Lowest Device Skew
of 35 ps and a part-to-part skew of max. 250 ps. To ensure low skew
clock signals in the application, both outputs of any differential
output pair need to be terminated identically, even if only one output
is used. When fewer than all nine output pairs are used, identical
termination of all output pairs within the output bank is
recommended. If an entire output bank is not used, it is
recommended to leave all of these outputs open and unterminated.
This will reduce the device power consumption while maintaining
minimum output skew.
Power Supply Bypassing
differential architecture of the MC100ES6111 supports low noise
signal operation at high frequencies. In order to maintain its superior
signal quality, all V
ceramic capacitors connected to GND. If the spectral frequencies of
the internally generated switching noise on the supply pins cross the
series resonant point of an individual bypass capacitor, its overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination shown
ensures that a low impedance path to ground exists for frequencies
well above the noise bandwidth.
The MC100ES6111 guarantees low output-to-output bank skew
The MC100ES6111 is a mixed analog/digital product. The
V
CC
Figure 4. V
33...100 nF
CC
pins should be bypassed by high-frequency
CC
Power Supply Bypass
©2009 Integrated Device Technology, Inc.
0.1 nF
V
CC
MC100ES6111