PI6C41202LX Pericom Semiconductor, PI6C41202LX Datasheet - Page 4

• Manufacturer Part Number: PI6C41202LX
• Manufacturer: Pericom Semiconductor
• Type: Clock Driverr

Specifications of PI6C41202LX

• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 266MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Not Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Table 3a. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following
a rising and falling input clock edge as shown in figure1. In the active mode, the state
of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3b.
Table 3b. Clock Input Function Table
Note:
*PI6C41204 and PI6C41204A have four differential outputs. Q0 through Q3 and nQ0 through nQ3.
PI6C41202 has two differential outputs. Q0 through Q1 and nQ0 through nQ1.
CLK0, CLK1
nQ0 - nQ3*
C
L
Q0 - Q3*
CLK_EN
K
0
0
1
1
_
E
N
C
L
K
n I
0
p
r o
0
1
u
C
s t
C
L
L
K
K
n I
0
0
1
1
_
1
S
p
u
E
s t
L
Disabled
S
l e
c e
Figure 1. CLK_EN Timing Diagram
C
C
C
C
e t
Q
L
L
L
L
d
0
K
K
K
K
S
H
L
0
1
0
1
h t
o
O
G I
r u
u r
W
H
e c
Q
* 3
D
D
O
Q
a s i
a s i
u
p t
0
l b
l b
E
E
4
u
h t
a n
a n
d e
d e
s t
u r
l b
l b
n
;
;
Q
d e
d e
Q
L
L
0
O
O
* 3
H
L
h t
W
W
O
G I
u r
O
W
H
u
n
p t
Q
u
* 3
s t
D
D
n
Q
a s i
a s i
0
l b
l b
E
E
h t
a n
a n
d e
d e
u r
l b
l b
;
;
d e
d e
Enabled
n
H
H
Q
LVCMOS to LVPECL Driver
G I
G I
* 3
H
H
PS8626D
PI6C4120x
05/11/05