PI6C41204LEX Pericom Semiconductor, PI6C41204LEX Datasheet - Page 3

• Manufacturer Part Number: PI6C41204LEX
• Description: Clock Drivers & Distribution 2:4 LVCMOS to LVPECL Clock Gen
• Manufacturer: Pericom Semiconductor
• Type: Clock Driverr

Specifications of PI6C41204LEX

• Number Of Clock Inputs: 2
• Output Logic Level: LVPECL
• Mode Of Operation: Single-Ended
• Output Frequency: 266MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 20
• Max Output Freq: 266 MHz
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Multiply / Divide Factor: 2:1
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TSSOP-20
• Lead Free Status / RoHS Status: Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Table 2. Pin Characteristics
Table 3a. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following
a rising and falling input clock edge as shown in figure1. In the active mode, the state
of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3b.
R
P
R
S
U
C
P
y
L
L
C
U
m
L
K
I
L
D
08-0304
N
0
0
1
1
b
L
_
O
l o
U
E
W
P
N
N
I
p n
I
p n
C
I
t u
p n
L
t u
K
P
t u
R
n I
C
l l u
0
0
1
1
_
s e
P
S
p
p a
p u
t s i
u
E
u
s t
d l l
a
L
P
r o
t i c
R
a
o
s e
a r
n a
w
t s i
m
n
e c
e
r o
S
e t
l e
r
c e
C
C
C
C
e t
C
C
L
L
L
L
d
L
K
K
C
K
K
L
C
S
K
L
K
0
1
0
1
L
o
K
_
K
r u
_
S
E
, 0
1
e c
E
N
L
T
D
D
e
Q
a s i
a s i
t s
0
l b
l b
E
E
3
h t
a n
C
a n
d e
d e
u r
o
l b
l b
n
;
;
d e
d e
d
Q
L
L
t i
O
O
* 3
o i
W
W
s n
O
u
p t
u
s t
D
D
n
Q
a s i
a s i
M
0
l b
l b
E
E
i
. n
h t
a n
a n
d e
d e
u r
l b
l b
;
;
d e
d e
n
H
H
Q
LVCMOS to LVPECL Driver
G I
G I
* 3
H
H
T
3
2
8
8
y
2 .
7 .
0
0
. p
PI6C41204/PI6C41204A
M
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PS8626E
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11/18/08