ICS8305AG IDT, Integrated Device Technology Inc, ICS8305AG Datasheet - Page 6

• Manufacturer Part Number: ICS8305AG
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8305AG

• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant

AC Electrical Characteristics
Table 5A. AC Characteristics, V
All parameters measured at ƒ ≤ 350MHz unless noted otherwise.
NOTE 1A: Measured from the V
NOTE 1B: Measured from the differential input crossing point to V
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions.
Using the same type of input on each device, the output is measured at V
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V
For NOTES, see Table 5A above.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Parameter
f
tp
tsk(o)
tsk(pp)
tjit
t
odc
t
t
Parameter
f
tp
tsk(o)
tsk(pp)
tjit
t
odc
t
t
MAX
R
EN
DIS
MAX
R
EN
DIS
ICS8305
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
LH
LH
/ t
/ t
F
F
Symbol
Output Frequency
Propagation
Delay,
Low to High
Output Skew; NOTE 2, 6
Part-to-Part Skew; NOTE 3, 6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
Output Rise/Fall Time; NOTE 4
Output Duty Cycle
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Symbol
Output Frequency
Propagation
Delay,
Low to High
Output Skew; NOTE 2, 6
Part-to-Part Skew; NOTE 3, 6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
Output Rise/Fall Time; NOTE 4
Output Duty Cycle
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
DD
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
/2 of the input to V
DD
DD
= V
= 3.3V ± 5%, V
DDO
= 3.3V ± 5%, T
DDO
Ref = LVCMOS_CLK, ƒ ≤ 300MHz
Ref = LVCMOS_CLK, ƒ ≤ 300MHz
Measured on the Rising Edge
Measured on the Rising Edge
/2 of the output.
DDO
Test Conditions
Ref = CLK/nCLK
Test Conditions
Ref = CLK/nCLK
= 2.5V ± 5%, T
20% to 80%
20% to 80%
DDO
A
6
= 0°C to 70°C
/2 of the output.
DDO
/2.
A
= 0°C to 70°C
Minimum
Minimum
ICS8305AG REV. C OCTOBER 23, 2008
1.75
100
100
1.8
45
45
44
44
Typical
Typical
0.04
0.04
Maximum
Maximum
DDO
2.75
350
700
700
350
800
700
2.9
35
55
55
35
56
56
5
5
5
5
/2.
Units
Units
MHz
MHz
ns
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps
ns
ns
%
%
%
%