ICS852911AVI IDT, Integrated Device Technology Inc, ICS852911AVI Datasheet
ICS852911AVI
Specifications of ICS852911AVI
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ICS852911AVI Summary of contents
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G D ENERAL ESCRIPTION The ICS852911I is a low skew, 1-to-9 Differential-to-HSTL Fanout Buffer. The ICS852911I has two selectable clock inputs which can accept most differential input levels. Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS852911I ...
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ABLE IN ESCRIPTIONS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA Storage Temperature, T -65°C to 150°C STG T 4A. P ...
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T 4D. HSTL DC C ABLE HARACTERISTICS ...
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P ARAMETER 3.3V±0.3V 1. DDO HSTL GND 0V 3.3V C /1.6V 3. ORE TO UTPUT OAD nQx Qx nQy Qy t sk( UTPUT KEW nHSTL_CLK, nPECL_CLK HSTL_CLK, PECL_CLK nQ0:nQ8 Q0:Q8 t ...
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IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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IFFERENTIAL LOCK NPUT NTERFACE The HSTL_CLK/nHSTL_CLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both V V must meet the V and V input requirements. Figures OH PP CMR show interface ...
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LVPECL LOCK NPUT NTERFACE The PECL_CLK/nPECL_CLK accepts LVPECL, CML, SSTL and other differential signals. Both V SWING the V and V input requirements. Figures CMR show interface examples for the PECL_CLK/nPECL_CLK input driven ...
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S E CHEMATIC XAMPLE Figure 4 shows a schematic example of ICS852911I. In this example, the input is driven by an ICS HiPerClockS HSTL VCCO Ohm Ohm HSTL Driv (U1-8) (U1-15) ...
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This section provides information on power dissipation and junction temperature for the ICS852911I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS852911I is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. F IGURE T o calculate worst case power dissipation into the ...
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ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs ...
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ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MS-018 852911AVI D IFFERENTIAL PLCC EAD ACKAGE IMENSIONS ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...