ICS853111BY IDT, Integrated Device Technology Inc, ICS853111BY Datasheet - Page 8
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ICS853111BY
Manufacturer Part Number
ICS853111BY
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.ICS853111BY.pdf
(20 pages)
Specifications of ICS853111BY
Lead Free Status / RoHS Status
Not Compliant
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Figure 1A shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
W
Figure 1B shows an example of the differential input that can
be wired to accept single ended LVPECL levels. The reference
voltage level V
IDT
W
ICS853111B
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
IRING THE
IRING THE
™
/ ICS
™
1-TO-10, LVPECL/ECL FANOUT BUFFER
D
D
BB
IFFERENTIAL
IFFERENTIAL
generated from the device is connected to the
F
IGURE
I
I
NPUT TO
NPUT TO
1B. S
F
IGURE
INGLE
A
Single Ended Clock Input
A
A
PPLICATION
CCEPT
CCEPT
1A. S
E
NDED
CLK_IN
INGLE
S
S
0.1uF
INGLE
LVPECL S
INGLE
C1
C1
0.1u
E
NDED
CC
/2 is
E
V_REF
E
NDED
NDED
I
S
NFORMATION
IGNAL
IGNAL
8
LVPECL L
LVCMOS L
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
negative input. The C1 capacitor should be located as close as
possible to the input pin.
PCLK
V
nPCLK
R1
1K
R2
1K
D
D
BB
RIVING
V
RIVING
CC
V
PCLKx
nPCLKx
CC
D
D
IFFERENTIAL
IFFERENTIAL
EVELS
EVELS
I
I
NPUT
NPUT
ICS853111BY REV. C JANUARY 13, 2009
CC
= 3.3V, V_REF should be 1.25V