IDTMC100ES6221AE IDT, Integrated Device Technology Inc, IDTMC100ES6221AE Datasheet - Page 6

• Manufacturer Part Number: IDTMC100ES6221AE
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of IDTMC100ES6221AE

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TQFP EP
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 52
• Quiescent Current: 160mA
• Lead Free Status / RoHS Status: Compliant

IDT™ Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6221
Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
6
Table 7. AC Characteristics (ECL: V
MC100ES6221
Clock Input Pair CLK0, CLK0 (PECL or ECL differential signals)
Clock Input Pair CLK1, CLK1 (HSTL differential signals)
PECL/ECL Clock Outputs (Q0–19, Q0–19)
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. V
3. V
4. V
5. V
6. Output pulse skew is the absolute difference of the propagation delay times: | t
Symbol
V
t
t
V
JIT(CC)
t
t
sk(PP)
V
DC
f
f
O(P-P)
SK(P)
V
sk(O)
t
device-to-device skew.
V
propagation delay, device and part-to-part skew.
skew. Only applicable to CLKB.
range and the input swing lies within the V
device and part-to-part skew.
CLK
t
CLK
t
CMR
V
r
PD
PD
DIF
, t
PP
PP
CMR
CMR
DIF
X
X
Q
f
(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V
(AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including t
(AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including t
(AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
(AC) range and the input swing lies within the V
Differential Input Voltage
Differential Input Crosspoint Voltage
Input Frequency
Propagation Delay CLK0 to Q0-19
Differential Input Voltage
Differential Input Crosspoint Voltage
Input Frequency
Propagation Delay CLK1 to Q0–19
Differential Output Voltage (peak-to-peak)
Output-to-Output Skew
Output-to-Output Skew (part-to-part)
Output Cycle-to-Cycle Jitter
Output Pulse Skew
Output Duty Cycle
Output Rise/Fall Time
Characteristics
(6)
(PECL: V
parts at one given T
(2)
(4)
(peak-to-peak)
(peak-to-peak)
EE
CC
=
DIF
= 3.3 V
–
(3)
(5)
3.3 V
(AC) specification. Violation of V
f
f
REF
REF
f
f
O
O
using CLK0
using CLK1
±
±
< 1.0 GHz
< 2.0 GHz
J
< 0.1 GHz
< 1.0 GHz
RMS (1σ)
, V
PP
5% or V
5% or V
CC
(AC) specification. Violation of V
PECL
ECL
, f
ref
EE
CC
V
TT
6
=
= 2.5 V
EE
0.375
.
–
TDB
49.5
45.0
Min
400
650
0.2
1.0
0.2
0.1
50
2.5 V
0
0
+ 1.0
±
±
X
pLH
5%, V
5%, V
(AC) or V
– t
0.68–0.9
0.630
0.250
Typ
pHL
540
780
50
30
50
50
EE
CC
|.
CMR
DIF
= GND, T
= GND) or
(AC) impacts the device propagation delay,
(AC) or V
V
V
CC
CC
–0.3 V
2000
1000
Max
50.5
55.0
670
950
100
270
300
250
350
J
1.3
1.3
50
Advanced Clock Drivers Devices
1
– 0.3
– 1.0
= 0°C to + 110°C)
PP
(AC) impacts the device
Freescale Semiconductor
MHz
MHz
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
PD
%
%
V
V
V
V
V
V
V
and device-to-device
PD
Differential
Differential
Differential
Differential
Differential
Differential
DC
DC
20% to 80%
and
(1)
REF
REF
Condition
= 50%
= 50%
X
MC100ES6221
(AC)
NETCOM