IDTMPC9449AE IDT, Integrated Device Technology Inc, IDTMPC9449AE Datasheet - Page 4

• Manufacturer Part Number: IDTMPC9449AE
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of IDTMPC9449AE

• Number Of Clock Inputs: 3
• Output Frequency: 200MHz
• Output Logic Level: LVCMOS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVPECL
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

MPC9449
3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER
Table 5. DC Characteristics (V
Table 6. AC Characteristics (V
1. The MPC9449 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
2. V
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. V
3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition.
Symbol
Symbol
V
V
t
t
t
t
t
PLH
t
PLZ, HZ
PZL, LZ
JIT(CC)
Z
P, REF
t
CMR
I
CMR
sk(PP)
t
V
f
V
V
V
t
sk(O)
t
V
CCQ
transmission line to a termination voltage of V
and the input swing lies within the V
sk(P)
and the input swing lies within the V
V
max
f
OUT
I
r
r
OH
IN
ref
, t
, t
PP
OL
PP
IH
CMR
CMR
IL
,
f
f
HL
(2)
(2)
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input High Voltage
Input Low Voltage
Output High Voltage
Peak-to-Peak Input Voltage
Common Mode Range
Output Low Voltage
Output Impedance
Input Current
Maximum Quiescent Supply Current
Peak-to-Peak Input Voltage
Common Mode Range
Output Frequency
Input Frequency
Reference Input Pulse Width
CCLK0, CCLK1 Input Rise/Fall Time
Output-to-Output Skew
Same Frequency
Different Frequencies
Device-to-Device Skew
Output Pulse Skew
Propagation Delay
Output Disable Time
Output Enable Time
Output Rise/Fall Time
Cycle-to-Cycle Jitter
Characteristics
Characteristics
(3)
CCLK0 or CCLK1 to any Q
CC
CC
= 3.3 V ± 5%, T
= 3.3 V ± 5%, T
PP
PP
(DC) specification.
(AC) specification. Violation of V
PCLK to any Q
PCLK, PCLK
PCLK, PCLK
PCLK, PCLK
PCLK, PCLK
TT
OE to any Q
OE to any Q
Qa outputs
Qb outputs
Qd outputs
Qc outputs
. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
All outputs
All outputs
RMS (1 σ)
A
A
= –40
= –40
°
°
C to 85°C)
C to 85°C)
Min
Min
250
400
2.0
2.4
1.0
1.0
1.5
1.0
1.0
0.1
0
0
TT
.
CMR
(1)
or V
14 – 17
PP
TBD
Typ
Typ
2.5
3.0
3.0
impacts propagation delay.
V
V
V
CC
CC
CC
±200
1000
Max
0.55
0.30
Max
200
200
100
200
300
250
0.8
1.0
5.0
5.0
1.0
10
50
50
50
11
11
+ 0.3
–0.6
–0.6
MHz
MHz
Unit
Unit
mV
mA
mV
µA
ns
ns
ps
ps
ps
ps
ps
ps
ns
ps
ns
ns
ns
ns
ns
ps
V
V
V
V
V
V
Ω
V
LVCMOS
LVCMOS
I
LVPECL
LVPECL
I
I
V
All V
LVPECL
LVPECL
0.8 to 2.0 V
DC
0.55 to 2.4 V
OH
OL
OL
IN
REF
= 24 mA
= 12 mA
= –24 mA
= V
CC
Condition
Condition
CC
= 50%
Pins
or GND
CMR
CMR
(1)
range
range