ICS8344AYI-01 IDT, Integrated Device Technology Inc, ICS8344AYI-01 Datasheet - Page 9

• Manufacturer Part Number: ICS8344AYI-01
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8344AYI-01

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 200MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

F
D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
F
F
IDT
IGURE
PP
IGURE
IGURE
IFFERENTIAL
ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
™
and V
2.5V
/ ICS
HCSL
3.3V
2C. H
2A. H
2E. H
*Optional – R3 and R4 can be 0Ω
1.8V
™
CMR
LVPECL
LVCMOS/LVTTL FANOUT BUFFER
input requirements. Figures 2A to 2F show interface
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
D
D
H
D
*R3
*R4
I
RIVEN BY A
I
RIVEN BY AN
I
I
RIVEN BY A
P
P
P
P
C
ER
ER
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
C
Zo = 50 Ohm
Zo = 50 Ohm
33
33
C
C
C
LOCK
LOCK
LOCK
LOCK
I
NPUT
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL D
S CLK/nCLK I
S CLK/nCLK I
S LVHSTL D
3.3V HCSL D
S CLK/nCLK I
IDT O
R1
50
3.3V
R3
125
I
NTERFACE
R1
84
R1
50
PEN
R2
50
R4
125
SWING
R2
84
E
MITTER
RIVER
CLK
nCLK
and V
R2
50
RIVER
NPUT
NPUT
CLK
nCLK
NPUT
3.3V
RIVER
3.3V
CLK
nCLK
HiPerClockS
Input
OH
HiPerClockS
Input
3.3V
must meet the
HiPerClockS
Input
9
F
component to confirm the driver termination requirements. For
example in Figure 2A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
F
F
IGURE
IGURE
IGURE
2.5V
3.3V
3.3V
SSTL
2D. H
2B. H
LVDS_Driv er
2F. H
LVPECL
D
D
D
I
RIVEN BY A
I
RIVEN BY A
I
RIVEN BY A
P
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
ER
Zo = 60Ω
Zo = 60Ω
C
C
C
LOCK
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
ICS8344AYI-01 REV. B SEPTEMBER 24, 2007
3.3V LVDS D
3.3V LVPECL D
S CLK/nCLK I
2.5V SSTL D
S CLK/nCLK I
S CLK/nCLK I
R1
50
R3
50
R3
120
2.5V
R1
120
R2
50
R1
100
R4
120
R2
120
CLK
nCLK
3.3V
RIVER
RIVER
NPUT
NPUT
NPUT
HiPerClockS
RIVER
Input
CLK
nCLK
PRELIMINARY
CLK
nCLK
3.3V
3.3V
HiPerClockS
Receiv er