ICS8545BGT IDT, Integrated Device Technology Inc, ICS8545BGT Datasheet - Page 11

• Manufacturer Part Number: ICS8545BGT
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8545BGT

• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 650MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8545.
Equations and example calculations are also provided.
1.
The total power dissipation for the ICS8545 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resitance
IDT™ / ICS™ LVDS FANOUT BUFFER
Linear Feet per Minute
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
ICS8545
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Power Dissipation.
•
Power (core)
The equation for Tj is as follows: Tj = θ
Tj = Junction Temperature
θ
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
70°C + 0.173W * 66.6°C/W = 81.5°C. This is well below the limit of 125°C.
JA
A
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
MAX
= V
DD_MAX
θ
JA
for 20 Lead TSSOP, Forced Convection
* I
DD_MAX
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
JA
= 3.465V * 50mA = 173.25mW
* Pd_total + T
θ
114.5°C/W
JA
73.2°C/W
A
by Velocity
0
11
98.0°C/W
66.6°C/W
200
JA
must be used. Assuming a moderate
ICS8545BG REV. D OCTOBER 28, 2008
88.0°C/W
63.5°C/W
500