ICS87008AGIT IDT, Integrated Device Technology Inc, ICS87008AGIT Datasheet - Page 10

• Manufacturer Part Number: ICS87008AGIT
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS87008AGIT

• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Not Compliant

W
87008AGI
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
R
I
CLK I
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
ground.
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
CLK to ground.
PCLK/nPCLK I
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1k
be tied from PCLK to ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
NPUTS
ECOMMENDATIONS FOR
IRING THE
NPUT
:
:
ONTROL
NPUT
D
NPUT
IFFERENTIAL
:
resistor can be used.
resistor can be tied from the CLK input to
P
:
INS
:
U
NUSED
I
F
NPUT TO
IGURE
Single Ended Clock Input
resistor can be tied from
I
1. S
NPUT AND
A
A
CLK_IN
PPLICATION
CCEPT
INGLE
0.1uF
D
C1
IFFERENTIAL
resistor can
E
O
C1
0.1u
S
NDED
UTPUT
V_REF
INGLE
DD
www.idt.com
/2 is
S
IGNAL
P
R1
1K
V_REF
R2
1K
E
10
INS
I
NDED
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
O
LVCMOS O
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
-
D
1K
V
TO
R1
1K
R2
UTPUTS
RIVING
CC
VDD
+
-
L
-LVCMOS/LVTTL C
EVELS
CLK
nCLK
D
:
IFFERENTIAL
UTPUT
:
I
NPUT
DD
= 3.3V, V_REF should be 1.25V
L
OW
LOCK
ICS87008I
S
KEW
G
REV. B JULY 31, 2010
ENERATOR
, 1-
TO
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