ICS8737AG-11T IDT, Integrated Device Technology Inc, ICS8737AG-11T Datasheet
ICS8737AG-11T
Specifications of ICS8737AG-11T
Related parts for ICS8737AG-11T
ICS8737AG-11T Summary of contents
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G D ENERAL ESCRIPTION The ICS8737- low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The ICS8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept ...
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ABLE IN ESCRIPTIONS ...
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T 3A ABLE ONTROL NPUT UNCTION ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S y ...
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T 4D. LVPECL DC C ABLE HARACTERISTICS ...
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The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most ...
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P ARAMETER LVPECL V EE -1.3V ± 0.165V 3. UTPUT OAD EST IRCUIT nQx Qx nQy Qy tsk( UTPUT KEW nCLK, nPCLK CLK, PCLK nQAx, nQBx QAx, QBx t PD ...
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IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V generated by the bias resistors R1, R2 and C1. This bias ...
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IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show PP CMR interface examples for the ...
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LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING OH V input requirements. Figures show interface CMR examples for the PCLK/nPCLK input driven ...
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This section provides information on power dissipation and junction temperature for the ICS8737-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8737-11 is the sum of the core power plus the power ...
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Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 6. F IGURE T o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage ...
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ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains ...
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ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 8737AG- 3.3V LVPECL C IFFERENTIAL TO TSSOP EAD ACKAGE IMENSIONS ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...