ICS83908AGI-02 IDT, Integrated Device Technology Inc, ICS83908AGI-02 Datasheet - Page 11

• Manufacturer Part Number: ICS83908AGI-02
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS83908AGI-02

• Number Of Clock Inputs: 3
• Mode Of Operation: Single-Ended
• Output Frequency: 200MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Not Compliant

C
Figure 1 shows an example of ICS83908I-02 crystal interface
with a parallel resonant crystal. The frequency accuracy can
be fine tuned by adjusting the C1 and C2 values. For a parallel
crystal with loading capacitance CL = 18pF, we suggest C1
and C2 = 15pF to start with. These values may be slightly fine
tuned further to optimize the frequency accuracy for different
LVCMOS
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
IDT
RYSTAL
ICS83908I-02
LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER
™
/ ICS
™
I
LVCMOS FANOUT BUFFER
NPUT
TO
XTAL I
I
NTERFACE
NTERFACE
F
IGURE
18pF Parallel Crystal
2. G
VDD
Ro
ENERAL
A
X1
PPLICATION
D
F
IAGRAM FOR
IGURE
Rs
Zo = Ro + Rs
1. Crystal Input Interface
C2
15p
Zo = 50
LVCMOS D
11
C1
15p
I
NFORMATION
board layouts. Slightly increasing the C1 and C2 values will
slightly reduce the frequency. Slightly decreasing the C1 and
C2 values will slightly increase the frequency. For the oscillator
circuit below, R1 can be used, but is not required. For new
designs, it is recommended that R1 not be used.
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
and R2 can be 100 . This can also be accomplished by removing
R1 and making R2 50 .
R1 (optional)
VDD
0
RIVER TO
R1
R2
.1uf
XTAL I
XTAL_IN
XTAL_OUT
XTAL_IN
XTAL_OUT
ICS83908AGI-02 REV. A FEBRUARY 13, 2009
NPUT
I
NTERFACE
applications, R1