854054AGLF IDT, Integrated Device Technology Inc, 854054AGLF Datasheet - Page 7

• Manufacturer Part Number: 854054AGLF
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Multiplexerr

Specifications of 854054AGLF

• Number Of Clock Inputs: 4
• Mode Of Operation: Differential
• Output Frequency: 2800MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/LVPECL/SSTL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
R
I
PCLK/nPCLK I
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1k resister can be tied
from PCLK to ground.
S
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1k
854054AG
NPUTS
ELECT
ECOMMENDATIONS FOR
IRING THE
P
:
INS
:
D
NPUT
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
:
U
resister can be used.
NUSED
I
F
NPUT TO
IGURE
Single Ended Clock Input
I
NPUT
1. S
A
A
www.icst.com/products/hiperclocks.html
PPLICATION
CCEPT
INGLE
P
INS
E
C1
0.1u
S
NDED
V_REF
INGLE
DD
/2 is
S
IGNAL
E
D
7
I
NDED
IFFERENTIAL
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
D
1K
R1
1K
R2
RIVING
VDD
L
EVELS
nPCLK
PCLK
D
IFFERENTIAL
-
TO
-LVDS C
I
NPUT
DD
= 3.3V, V_REF should be 1.25V
LOCK
ICS854054
M
REV. A MARCH 29, 2006
ULTIPLEXER
4:1