5T93GL101PFI IDT, Integrated Device Technology Inc, 5T93GL101PFI Datasheet - Page 10

• Manufacturer Part Number: 5T93GL101PFI
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of 5T93GL101PFI

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 450MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Quiescent Current: 295mA
• Lead Free Status / RoHS Status: Not Compliant

NOTES:
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the SEL pin should be toggled
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater
NOTES:
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the FSEL pin should
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater
IDT5T93GL101
2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II
and FSEL asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock.
than or equal to the minimum DC differential specified in the datasheet.
be asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock.
than or equal to the minimum DC differential specified in the datasheet.
FSEL Operation for When Opposite Clock Dies
FSEL Operation for When Current Clock Dies
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INDUSTRIAL TEMPERATURE RANGE