87354AMILF IDT, Integrated Device Technology Inc, 87354AMILF Datasheet - Page 8

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87354AMILF

Manufacturer Part Number
87354AMILF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Dividerr
Datasheet

Specifications of 87354AMILF

Number Of Clock Inputs
1
Mode Of Operation
Differential
Output Logic Level
LVPECL
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
SOIC N
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Compliant
T
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50
87354AMI
RTT =
ERMINATION FOR
((V
FOUT
F
OH
IGURE
+ V
OL
3A. LVPECL O
) / (V
1
CC
3.3V LVPECL O
Z
Z
– 2)) – 2
o
o
transmission lines. Matched imped-
= 50
= 50
Z
o
50
UTPUT
T
RTT
ERMINATION
50
UTPUT
V
CC
FIN
- 2V
www.idt.com
8
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT
F
IGURE
3.3V LVPECL C
3B. LVPECL O
Z
Z
o
o
= 50
= 50
÷4/÷5 D
125
84
UTPUT
3.3V
LOCK
ICS87354I
125
84
IFFERENTIAL
T
ERMINATION
REV. A AUGUST 5, 2010
G
FIN
ENERATOR
-
TO
-

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