ICS8536AG-01T IDT, Integrated Device Technology Inc, ICS8536AG-01T Datasheet - Page 12

• Manufacturer Part Number: ICS8536AG-01T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8536AG-01T

• Number Of Clock Inputs: 3
• Output Frequency: 700MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Not Compliant

F
D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both V
meet the V
show interface examples for the HiPerClockS CLK/nCLK input
driven by the most common driver types. The input interfaces
suggested here are examples only. Please consult with the
F
IDT
F
IGURE
IGURE
IGURE
IFFERENTIAL
ICS8536-01
LOW SKEW, 1-TO-6, CRYSTAL/LVCMOS/DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
™
2.5V
/ ICS
HCSL
3.3V
4C. H
4A. H
4E. H
*Optional – R3 and R4 can be 0
1.8V
™
LVPECL
3.3V, 2.5V LVPECL FANOUT BUFFER
PP
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
D
D
H
and V
D
*R3
*R4
I
RIVEN BY A
I
RIVEN BY AN
I
I
RIVEN BY A
P
P
P
P
C
ER
ER
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
C
33
33
CMR
C
C
C
LOCK
LOCK
LOCK
LOCK
input requirements. Figures 4A to 4F
I
NPUT
Zo = 50
Zo = 50
3.3V LVPECL D
S CLK/nCLK I
S CLK/nCLK I
S LVHSTL D
3.3V HCSL D
S CLK/nCLK I
IDT O
R1
50
3.3V
R3
125
I
NTERFACE
R1
84
R1
50
PEN
R2
50
R4
125
R2
84
E
MITTER
RIVER
CLK
nCLK
R2
50
RIVER
NPUT
NPUT
CLK
nCLK
NPUT
3.3V
SWING
RIVER
3.3V
CLK
nCLK
HiPerClockS
Input
and V
HiPerClockS
Input
3.3V
HiPerClockS
Input
OH
must
12
F
F
F
vendor of the driver component to confir m the driver
termination requirements. For example in Figure 4A, the input
termination applies for IDT HiPerClockS open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
IGURE
IGURE
IGURE
2.5V
3.3V
3.3V
SSTL
4B. H
4D. H
LVDS_Driv er
4F. H
LVPECL
D
D
D
I
RIVEN BY A
I
RIVEN BY A
I
RIVEN BY A
P
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
ER
Zo = 60
Zo = 60
C
C
C
LOCK
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
ICS8536AG-01 REV. A FEBRUARY 24, 2009
3.3V LVPECL D
3.3V LVDS D
S CLK/nCLK I
S CLK/nCLK I
2.5V SSTL D
S CLK/nCLK I
R1
50
R3
50
R3
120
2.5V
R1
120
R2
50
R1
100
R4
120
CLK
nCLK
R2
120
3.3V
RIVER
RIVER
NPUT
NPUT
NPUT
HiPerClockS
RIVER
Input
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
Receiv er