ICS870S208BKT IDT, Integrated Device Technology Inc, ICS870S208BKT Datasheet - Page 4

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ICS870S208BKT

Manufacturer Part Number
ICS870S208BKT
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Dividerr
Datasheet

Specifications of ICS870S208BKT

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
250MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Not Compliant
S
If a CLK_SEL, DIV_SEL, or OE event happens after a clock
has stopped , but before the input bad flag has been set (during
the ~200ns detect period) the SELECT change will not take
effect until the internal bad flag has been set. The output will
T
IDT
N
, 9
ABLE
WITCH
ICS870S208
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
O
N
1
1
1
T
1
1
2
3
/ ICS
u
, 6
, 0
, 4
: E
, 2
, 3
, 6
, 0
m
1
1
1
2
2
2
2
2
1. P
2
3
4
5
6
7
8
1
2
7
0
2
3
4
8
9
1
1
1
2
b
3
2
2
P
, 5
, 1
, 5
D
7
1
9
8
r e
u
LVCMOS FANOUT BUFFER W/DIVIDER
IN
u l l
3
URING AN
2
p
D
a
ESCRIPTIONS
Q
D
D
Q
Q
Q
n
C
d
V I
V I
A
B
O
O
O
O
O
O
n
L
A
B
O
O
n
N
C
V
V
CLK_SEL
C
G
, 0
C
K
, 0
C
P
, 3
, 3
E
E
E
E
E
E
V
_
E
E
_
a
L
D
D
L
N
L
_
_
_
_
_
u
S
D
L
S
D
D
_
_
m
_
_
K
Output
K
Q
Q
K
S
Q
O
O
Q
D
A
B
B
d l l
K
D
A
A
B
I
CLK0
CLK1
E
E
A
B
0
1
A
B
e
NPUT
A
0
E
B
1
A
B
0
2
3
0
2
3
1
1
L
L
o
, 1
, 1
L
B
A
2
2
w
n
r
O
O
P
P
P
P
B
f e
n I
n I
n I
n I
n I
n I
n I
n I
n I
n I
n I
n I
n I
n I
n I
o
o
o
o
u
u
r e
AD
p
p
p
w
p
p
p
p
w
w
w
p
p
p
p
p
p
p
p
p t
p t
t u
t u
t u
t u
t u
t u
t u
t u
t u
t u
t u
t u
t u
t u
t u
r e
r e
r e
r e
t u
t u
o t
D
T
n i
Detect, 200ns
y
ETECT
e t
p
P
P
P
P
P
Input Bad
e
P
P
P
P
P
P
P
P
P
P
n r
u
u
u
u
u
d l l
d l l
d l l
d l l
d l l
u
u
u
u
u
u
u
u
u
u
l a
F
u l l
u l l
u l l
u l l
u l l
u l l
u l l
u l l
u l l
u l l
o
o
o
o
o
IGURE
n i
w
w
w
w
w
p
p
p
p
p
p
p
p
p
p
p
n
n
n
n
n
t u
1G. CLK_SEL
e r
D
N
n I
P
C
N
n I
S
B
B
H
H
H
H
H
H
H
H
C
W
C
O
O
O
O
O
O
O
O
O
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o
u
a
a
e
o
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o l
o
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- i
- i
- i
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e v
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s
h
s
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n
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t n
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. Z
. Z
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. Z
t s i
p t
p t
p t
p t
p t
p t
p t
p t
p t
p t
k c
e
i t i
p
k
k
c
t r
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o r
n
o r
n i
n i
t u
t u
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t u
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t u
t u
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t u
y l
r o
i r
e v
L
L
L
L
L
L
L
L
n i
n i
A
B
s
V
V
V
V
V
V
V
V
e v
L
e v
s l
s l
t p
g
g
. s
e
g
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C
C
C
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C
C
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o
o
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e l
o r
n
n
n
n
n
n
n
n
o i
t r
t r
a
a
f
f
d
d
u
u
u
S
W
M
M
M
M
M
M
M
M
e r
e r
a
a
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a
a
a
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a
n
n
n i
n i
f i
t c
f i
p t
p t
p
u
n
e
b
b
b
b
b
b
b
b
O
O
O
O
O
O
O
O
e f
,
e f
k
k
q
q
g
p
g
n
e
u
u
e l
e l
e l
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e l
e l
e l
e l
n i
s
u
u
S
S
S
S
S
S
S
S
y l
. d
A
B
e r
e r
. s t
. s t
d
e
d
e
e
a T
p
f
f
f
f
f
f
f
f
f i
e l
f i
/
/
/
/
/
/
/
/
n
t n
t n
n
s
s
r o
r o
r o
r o
r o
r o
r o
r o
i p
4
u
e f
e f
L
L
b
y c
y c
u
u
L
L
L
L
L
L
L
L
WITH
c
. t
a i
. n
a i
V
V
V
V
V
V
V
V
V
V
e l
p
p
s t
Q
Q
Q
Q
Q
Q
Q
Q
e r
e r
go low after the input bad flag is set and follow the second
period of the new clock input. Although no glitches will occur,
due to the unknown state of the failing clock, a transition may
take up to 1us to execute.
W
c l
c l
C
C
p
p
T
T
T
T
T
T
T
T
d
d
A
A
A
A
B
B
B
B
, 2
t n
t n
y l
y l
C
M
M
T
T
T
T
T
T
T
T
v i
v i
h
o l
o l
0
1
2
3
0
1
2
3
L
L
L
L
L
L
L
L
B
a i
L
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e
s i
s i
O
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p
p
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o
o
o
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i
i
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i
i
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n i
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t n
t n
t n
t n
t n
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t n
t n
n i
u
u
u
u
u
u
u
u
, 0
I H
. s
. s
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p t
p t
p t
p t
p t
p t
p t
n
n i
n i
n
o l
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r e
r e
r e
r e
r e
r e
r e
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/
/
C
I
n
G
L
L
u
u
u
u
u
u
u
u
NPUT
f
p
p
f
k c
k c
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a f
h
r o
r o
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a r
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ICS870S208BK REV. A NOVEMBER 9, 2007
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