M48T128Y-70PM1TR STMicroelectronics, M48T128Y-70PM1TR Datasheet - Page 8

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M48T128Y-70PM1TR

Manufacturer Part Number
M48T128Y-70PM1TR
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of M48T128Y-70PM1TR

Bus Type
Parallel
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
32
Mounting
Through Hole
Date Format
DW:DM:M:Y
Time Format
HH:MM:SS
Lead Free Status / RoHS Status
Compliant
M48T128Y, M48T128V*
WRITE Mode
The M48T128Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
or W must return high for a minimum of t
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
8/22
A0-A16
E
W
DQ0-DQ7
A0-A16
E
W
DQ0-DQ7
tAVEL
tAVWL
tAVEL
tAVWL
EHAX
tWLQZ
from
tAVEH
tAVWH
tAVAV
VALID
tWLWH
tAVAV
VALID
tELEH
Chip Enable or t
the initiation of another READ or WRITE cycle.
Data-in must be valid t
WRITE and remain valid for t
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs t
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
WHAX
WLQZ
tEHDX
from WRITE Enable prior to
DVWH
tWHQX
after W falls.
tEHAX
tWHAX
prior to the end of
WHDX
AI02383
AI02382
afterward. G

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