LMH6581VS National Semiconductor, LMH6581VS Datasheet - Page 18

• Manufacturer Part Number: LMH6581VS
• Manufacturer: National Semiconductor

Specifications of LMH6581VS

• Array Configuration: 8x4
• Number Of Arrays: 1
• Screening Level: Industrial
• Pin Count: 48
• Package Type: TQFP
• Power Supply Requirement: Dual
• Lead Free Status / RoHS Status: Not Compliant

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USING OUTPUT BUFFERING TO ENHANCE BANDWIDTH
AND INCREASE REBIABILITY
The LMH6580/LMH6581 crosspoint switch can offer en-
hanced bandwidth and reliability with the use of external
buffers on the outputs. The bandwidth is increased by un-
loading the outputs and driving the high impedance of an
external buffer. See the Frequency Response 1 kΩ Load
curve in the Typical Performance section for an example of
bandwidth achieved with less loading on the outputs. For this
technique to provide maximum benefit a very high speed am-
plifier such as the LMH6703 should be used. As shown in
Figure 6 the resistor R
put and the buffer amplifier. This resistor will provide a load
for the crosspoint output buffer and reduce peaking caused
by the buffer input capacitance. A recommended value for
R
bandwidth, but also higher peaking. The optimum value of
R
tance of the buffer amplifier.
Besides offering enhanced bandwidth performance using an
external buffer provides greater system reliability. The first
advantage is to reduce thermal loading on the crosspoint
switch. This reduced die temperature will increase the life of
the crosspoint. The second advantage is enhanced ESD re-
liability. It is very difficult to build high speed devices that can
withstand all possible ESD events. With external buffers the
crosspoint switch is isolated from ESD events on the external
system connectors.
CROSSTALK
When designing a large system such as a video router
crosstalk can be a very serious problem. Extensive testing in
our lab has shown that most crosstalk is related to board lay-
out rather than occurring in the crosspoint switch. There are
many ways to reduce board related crosstalk. Using con-
trolled impedance lines is an important step. Using well de-
coupled power and ground planes will help as well. When
crosstalk does occur within the crosspoint switch itself it is
often due to signals coupling into the power supply pins. Using
appropriate supply bypassing will help to reduce this mode of
coupling. Another suggestion is to place as much grounded
copper as possible between input and output signal traces.
Care must be taken, though, not to influence the signal trace
impedances by placing shielding copper too closely. One oth-
er caveat to consider is that as shielding materials come
closer to the signal trace the trace needs to be smaller to keep
the impedance from falling too low. Using thin signal traces
will result in unacceptable losses due to trace resistance. This
effect becomes even more pronounced at higher frequencies
due to the skin effect. The skin effect reduces the effective
thickness of the trace as frequency increases. Resistive loss-
es make crosstalk worse because as the desired signal is
attenuated with higher frequencies crosstalk increases at
higher frequencies.
L
L
will depend greatly on board layout and the input capaci-
is 500Ω to 1000Ω. Higher values of R
FIGURE 6. Buffered Output
L
is placed between the crosspoint out-
L
will give higher
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DIGITAL CONTROL
Logic Pins
There are two modes for programing the LMH6580/
LMH6581, Serial Mode and Addressed Mode. The LMH6580/
LMH6581 have internal control registers that store the pro-
gramming states of the crosspoint switch. The logic is two
staged to allow for maximum programming flexibility. The first
stage of the control logic is tied directly to the crosspoint
switching matrix. This logic consists of one register for each
output that stores the on/off state and the address of which
input to connect to. These registers are not directly accessible
to the user. The second level of logic is another bank of reg-
isters identical to the first, but set up as shift registers. These
registers are accessed by the user via the serial input bus.
The LMH6580/LMH6581 is programmed via a serial input bus
with the support of four other digital control pins. The Serial
bus consists of a clock pin (CLK), a serial data in pin (DIN),
and a serial data out pin (D
chip select pin (CS). The chip select pin is active low. While
the chip select pin is high all data on the serial input pin and
clock pins is ignored. When the chip select pin is brought low
the internal logic is set to begin receiving data by the first
positive transition (0 to 1) of the clock signal. The chip select
pin must be brought low at least 5 ns before the first rising
edge of the clock signal. The first data bit is clocked in on the
next negative transition (1 to 0) of the clock signal. All input
data is read from the bus on the negative edge of the clock
signal. Once the last valid data has been clocked in, either the
Pin Name Level
CLK
CS
DATA IN
DATA
OUT
CFG
MODE
RST
BCST
Sensitive
Yes
Yes
Yes
Yes
Yes
Block Diagram
FIGURE 7.
OUT
Edge
Triggered
Yes
Yes
Yes
). The serial bus is gated by a
Triggered by
CLK rising
edge
CLK falling
edge
CLK rising
edge
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