LMH6580VS National Semiconductor, LMH6580VS Datasheet - Page 21

• Manufacturer Part Number: LMH6580VS
• Manufacturer: National Semiconductor

Specifications of LMH6580VS

• Array Configuration: 8x4
• Number Of Arrays: 1
• Screening Level: Industrial
• Pin Count: 48
• Package Type: TQFP
• Power Supply Requirement: Dual
• Lead Free Status / RoHS Status: Not Compliant

Addressed Mode Word Format
Bit 0 is first bit clocked into device.
DAISY CHAIN OPTION IN SERIAL MODE
The LMH6580/LMH6581 supports daisy chaining of the serial
data stream between multiple chips. This feature is available
only in the Serial Programming Mode. To use this feature se-
rial data is clocked into the first chip D
D
may share a chip select signal, or the second chip can be
enabled separately. When the chip select pin goes low on
both chips a double length word is clocked into the first chip.
As the first word is clocking into the first chip the second chip
is receiving the data that was originally in the shift register of
the first chip (invalid data). When a full 16 bits have been
clocked into the first chip the next clock cycle begins moving
the first frame of the new configuration data into the second
chip. With a full 32 clock cycles both chips have valid data and
the chip select pin of both chips should be brought high to
prevent the data from overshooting. A configure pulse will ac-
tivate the new configuration on both chips simultaneously, or
each chip can be configured separately. The mode, chip se-
lect, configure and clock pins of both chips can be tied to-
gether and driven from the same sources.
SPECIAL CONTROL PINS
The LMH6580/LMH6581 have two special control pins that
function independent of the serial control bus. One of these
pins is the reset (RST) pin. The RST pin is active high mean-
ing that at logic 1 level the chip is configured with all outputs
disabled and in a high impedance state. The RST pin pro-
grams all the registers with input address 0 and all the outputs
are turned off. In this configuration the device draws only 11-
mA. The RST pin can be used as a shutdown function to
reduce power consumption. The other special control pin is
the broadcast (BCST) pin. The BCST pin is also active high
and sets all the outputs to the on state connected to input 0.
This is sometimes referred to as broadcast mode, where input
0 is broadcast to all eight outputs.
THERMAL MANAGEMENT
The LMH6580/LMH6581 are high performance devices that
produce a significant amount of heat. With ±5V supplies, the
LMH6580/LMH6581 will dissipate approximately 0.5 W of
idling power with all outputs enabled. Idling power is calcu-
IN
pin is connected to the D
Output Address
LSB
0
OUT
MSB
1
pin of the first chip. Both chips
IN
pin, and the next chip
Input Address
LSB
2
3
21
MSB
4
lated based on the typical supply current of 50 mA and a 10V
supply voltage. This power dissipation will vary within the
range of 0.4 W to 0.6 W due to process variations. In addition,
each equivalent video load (150Ω) connected to the outputs
should be budgeted 30 mW of power. For a typical application
with one video load for each output this would be a total power
of 0.62 W. With a θ
being 27°C over the ambient temperature. A more aggressive
application would be two video loads per output which would
result in 0.74 W of power dissipation. This would result in a
33°C temperature rise. For heavier loading, the TQFP pack-
age thermal performance can be significantly enhanced with
an external heat sink and by providing for moving air ventila-
tion. Also, be sure to calculate the increase in ambient tem-
perature from all devices operating in the system case.
Because of the high power output of this device, thermal
management should be considered very early in the design
process. Generous passive venting and vertical board orien-
tation may avoid the need for fan cooling or heat sinks. Also,
the LMH6580/LMH6581 can be operated with a ±3.3V power
supply. This will cut power dissipation substantially while only
reducing bandwidth by about 10% (2 V
LMH6580/LMH6581 are fully characterized and factory tested
at the ±3.3V power supply condition for applications where
reduced power is desired.
PRINTED CIRCUIT LAYOUT
Generally, a good high frequency layout will keep power sup-
ply and ground traces away from the input and output pins.
Parasitic capacitances on these nodes to ground will cause
frequency response peaking and possible circuit oscillations
(see Application Note OA-15 for more information). If digital
control lines must cross analog signal lines (particularly in-
puts) it is best if they cross perpendicularly. National Semi-
conductor suggests the following evaluation boards as a
guide for high frequency layout and as an aid in device testing
and characterization:
Device
LMH6580
TRI-STATE
1 = TRI-STATE
0 = On
5
JA
Package
48–Pin
of 44 °C/W this will result in the silicon
Evaluation Board
Part Number
LMH730164EF
PP
output). The
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