LMH6584VV National Semiconductor, LMH6584VV Datasheet - Page 18

• Manufacturer Part Number: LMH6584VV
• Manufacturer: National Semiconductor

Specifications of LMH6584VV

• Array Configuration: 32x16
• Number Of Arrays: 1
• Screening Level: Industrial
• Pin Count: 144
• Package Type: LQFP
• Power Supply Requirement: Dual
• Lead Free Status / RoHS Status: Supplier Unconfirmed

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with higher frequencies crosstalk increases at higher frequen-
cies.
DIGITAL CONTROL
The LMH6584/LMH6585 has internal control registers that
store the programming states of the crosspoint switch. The
logic is two staged to allow for maximum programming flexi-
bility. The first stage of the control logic is tied directly to the
crosspoint switching matrix. This logic consists of one register
for each output that stores the on/off state and the address of
which input to connect to. These registers are not directly ac-
cessible by the user. The second level of logic is another bank
of registers identical to the first, but set up as shift registers.
These registers are accessed by the user via the serial input
bus. As described further below, there are two modes for pro-
graming the LMH6584/LMH6585, Serial Mode and Ad-
dressed Mode.
The LMH6584/LMH6585 are programmed via a serial input
bus with the support of four other digital control pins. The se-
rial bus consists of a clock pin (CLK), a serial data in pin
(D
by a chip select pin (CS). The chip select pin is active low.
While the chip select pin is high all data on the serial input pin
and clock pins is ignored. When the chip select pin is brought
low the internal logic is set to begin receiving data by the first
positive transition (0 to 1) of the clock signal. The chip select
pin must be brought low at least 5 ns before the first rising
edge of the clock signal. The first data bit is clocked in on the
next negative transition (1 to 0) of the clock signal. All input
data is read from the bus on the negative edge of the clock
signal. Once the last valid data has been clocked in, the chip
select pin must go high then the clock signal must make at
least one more low to high transition. Otherwise invalid data
will be clocked into the chip. The data clocked into the chip is
not transferred to the crosspoint matrix until the CFG pin is
pulsed high. This is the case regardless of the state of the
MODE pin. The CFG pin is not dependent on the state of the
chip select pin. If no new data is clocked into the chip subse-
quent pulses on the CFG pin will have no affect on device
operation.
IN
), and a serial data out pin (D
FIGURE 13. Block Diagram
Block Diagram
OUT
). The serial bus is gated
30045011
18
The programming format of the incoming serial data is se-
lected by the MODE pin. When the MODE pin is HIGH the
crosspoint can be programmed one output at a time by en-
tering a string of data that contains the address of the output
that is going to be changed (Addressed Mode). When the
MODE pin is LOW the crosspoint is in Serial Mode. In this
mode the crosspoint accepts a 40 bit array of data that pro-
grams all of the outputs. In both modes the data fed into the
chip does not change the chip operation until the configure
pin is pulsed high. The configure and mode pins are inde-
pendent of the chip select pin.
THREE WIRE VS. FOUR WIRE CONTROL
There are two ways to connect the serial data pins. The first
way is to control all four pins separately, and the second op-
tion is to connect the CFG and the CS pins together for a three
wire interface. The benefit of the four wire interface is that the
chip can be configured independently of the CS pin. This
would be an advantage in a system with multiple crosspoint
chips where all of them could be programmed ahead of time
and then configured simultaneously. The four wire solution is
also helpful in a system that has a free running clock on the
CLK pin. In this case, the CS pin needs to be brought high
after the last valid data bit to prevent invalid data from being
clocked into the chip.
The three wire option provides the advantage of one less pin
to control at the expense of having less flexibility with the
configure pin. One way around this loss of flexibility would be
if the clock signal is generated by an FPGA or microcontroller
where the clock signal can be stopped after the data is
clocked in. In this case the Chip Select function is provided
by the presence or absence of the clock signal.
SERIAL PROGRAMMING MODE
Serial programming mode is the mode selected by bringing
the MODE pin low. In this mode a stream of 96-bits programs
all 16 outputs of the crosspoint. The data is fed to the chip as
shown in the Serial Mode Data Frame tables below (four ta-
bles are shown to illustrate the pattern). The tables are ar-
ranged such that the first bit clocked into the crosspoint
register is labeled bit number 0. The register labeled Load
Register in the block diagram is a shift register. If the chip
select pin is left low after the valid data is shifted into the chip
and if the clock signal keeps running then additional data will
be shifted into the register, and the desired data will be shifted
out.
Also illustrated are the timing relationships for the digital pins
in the Timing Diagram for Serial Mode shown below. It is im-
portant to note that all the pin timing relationships are impor-
tant, not just the data and clock pins. One example is that the
Chip Select pin (CS) must transition low before the first rising
edge of the clock signal. This allows the internal timing circuits
to synchronize to allow data to be accepted on the next falling
edge. After the final data bit has been clocked in, the chip
select pin must go high, then the clock signal must make at
least one more low to high transition. As shown in the timing
diagram, the chip select pin state should always occur while
the clock signal is low. The configure (CFG) pin timing is not
so critical, but it does need to be kept low until all data has
been shifted into the crosspoint registers.