77V126L200TFGI IDT, Integrated Device Technology Inc, 77V126L200TFGI Datasheet - Page 21

• Manufacturer Part Number: 77V126L200TFGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 77V126L200TFGI

• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Diagnostic Control Register
Address: 0x02
IDT77V126L200
7
6
5
4
3
2
1, 0 R/W
Bit
1.
5
4
3
2
1
0
When Bits [1:0] in the Diagnostic Control Registers are set to 10, the PHY loopback mode works only if clock multiplier is 1x. For higher multiplies, these bits must be set to 01.
R/W
R/W
R/W
R/W
R/W
R/W
Type
sticky 0
sticky 0
sticky 0
sticky 0
sticky 0
sticky 0
0 = normal
0 = UTOPIA RxCLAV Operation Select
1 = tri-state
0 = normal
0 = normal
0 = normal
00 = normal
Initial State
Force TxCLAV Deassert
This feature can be used during line loopback mode to prevent cells from being passed across the Utopia bus for transmission.
The UTOPIA standard dictates that during cell mode operation, if the receive FIFO no longer has a complete cell available for
transfer from PHY, RxCLAV is deasserted following transfer of the last byte out of the PHY
to the upstream system. With this bit set, early deassertion of this signal will occur coincident with the end of Payload byte 44 (as
in octet mode for TxCLAV). This provides early indication to the upstream system of this impending condition.
Single/Multi-PHY Configuration Select
0 = single:
1 = Multi-PHY mode: Tri-state RxDATA, RxPARITY and RxSOC when RxEN = 1
RFLUSH = Clear Receive FIFO
This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC signals this completion by clearing this bit.
Insert Transmit Payload Error
Tells TC to insert cell payload errors in transmitted cells. This can be used to test error detection and recovery systems at desti-
nation station, or, under loopback control, at the local receiving station. This payload error is accomplished by flipping bit 0 of the
last cell payload byte.
Insert Transmit HEC Error
Tells TC to insert HEC error in Byte 5 of transmitted cells. This can be used to test error detection and recovery systems in down-
stream switches, or, under loopback control, the local receiving station. The HEC error is accomplished by flipping bit 0 of the
HEC byte.
Loopback Control
bit # 1
HEC error cell received Set when a HEC error is detected on received cell.
"Short Cell" Received
Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected when receiving Start-of-Cell
command bytes with fewer than 53 bytes between them."
Transmit Parity Error
If Bit 4 of the Master Control Register (Transmit Data Parity Check) is set, this interrupt flags a transmit data parity error con-
dition. Odd parity is used.
Receive Signal Condition change This interrupt is set when the received ’signal’ changes either from ’bad to good’ or from
’good to bad’.
Received Symbol Error Set when an undefined 5-bit symbol is received.
Receive FIFO Overflow Interrupt which indicates when the receive FIFO has filled and cannot accept additional data.
0 = "Standard UTOPIA RxCLAV"
1 = "Cell mode = Byte mode"
0
1
1
0
0
0 Normal mode (receive from network)
0 PHY Loopback
1 Line Loopback
1 PHY Loopback (with clock recovery)
Never tri-state RxDATA, RxPARITY and RxSOC
1
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Function
December 2004