IDT77V107L25PFI8 IDT, Integrated Device Technology Inc, IDT77V107L25PFI8 Datasheet - Page 14

• Manufacturer Part Number: IDT77V107L25PFI8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V107L25PFI8

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

2. Counters
(e.g. software drivers) in evaluating communications conditions. It is
anticipated that these counters will be polled from time to time (user
selectable) to evaluate performance.
cell count (without roll over) if the counter is read once/second. The
Symbol Error counter and HEC Error counter were given sufficient size
to indicate exact counts for low error-rate conditions. If these counters
overflow, a gross condition is occurring, where additional counter resolu-
tion does not provide additional diagnostic benefit.
Reading Counters
IDT77V107
Several condition counters are provided to assist external systems
The TxCell and RxCell counters are sized (16 bits) to provide a full
1.
!
!
!
!
– 8 bits
– counts all invalid 5-bit symbols received
– - 16 bits
– counts all transmitted cells
– - 16 bits
– counts all received cells, excluding idle cells and HEC errored
– 5 bits
– counts all HEC errors received
Select Register to the bit location corresponding to the desired
counter. This loads the High and Low Byte Counter Registers with
the selected counter’s value, and resets this counter to zero.
Symbol Error Counters
Transmit Cell Counters
Receive Cell Counters
Receive HEC Error Counters
Decide which counter value is desired. Write to the Counter
cells
1
2
3
4
5
6
7
8
7
8
10
9
14
3
Magnetics
4
13
Figure 15 Recommended Connection to Magnetics
5
AGND
12
16
15
AGND
1
2
C1
R3
R8
C2
R9
14 of 24
R1
R2
C3
the Counter Select Registers.
Line Side (Serial) Interface
PHY to Magnetics Interface
cabling is shown in the figure below. Note that the transmit signal is
somewhat attenuated in order to meet the launch amplitude specified by
the standards. The receive circuitry is designed to attenuate low
frequencies in order to compensate for the high frequency attenuation of
the cable.
to slightly different voltages. This is done so that the receiver does not
receive false signals in the absence of a real signal. This can be impor-
tant because the 77V107 does not disable error detection or interrupts
when an input signal is not present.
magnetics with sufficient bandwidth. Such a device can also operate
satisfactorily at 25.6 Mbps.
2.
Further reads may be accomplished in the same manner by writing to
A standard connection to 100
Also, the receive circuitry biases the positive and negative RX inputs
When connecting to UTP at 51.2 Mbps, it is necessary to use
R4
R5
value.
NOTE: Only one counter may be enabled at any time in the
Counter Select Register.
Read the Counter Registers (low byte and high byte) to get the
R6
AVDD
AGND
R7
R10
L1
TxD-
TxD+
RxD+
RxD-
and 120
IDT77V107
5362 drw 36
unshielded twisted pair
December 2004
.