IDT77105L25TF IDT, Integrated Device Technology Inc, IDT77105L25TF Datasheet - Page 5

• Manufacturer Part Number: IDT77105L25TF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77105L25TF

• Data Rate: 25.6Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin
IDT77105
RxSOC
RxEmpty/RxClav
RxRef
V
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
GND
RxData6
RxData7
RxParity
RxClk
RxEnb
TxFull/TxCLAV
TxSOC
TxEnb
TxClk
TxParity
TxData7
TxData6
TxData5
TxData4
TxData3
TxData2
TxData1
TxData0
TxRef
Reset
INT
AD7
AD6
VCC
AD5
AD4
AD3
AD2
AD1
AD0
GND
CS
CC
Name
O
O
O
—
O
O
O
O
O
O
—
O
O
O
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I
I/O
UTOPIA bus
UTOPIA bus
UTOPIA bus
Power plane
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
Ground plane
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
control
control
Utility bus
Utility bus
Power plane
Utility bus
Utility bus
Utility bus
Utility bus
Utility bus
Utility bus
Ground plane
Utility bus
Interfaces to
Receive Start of Cell signal.
Receive Empty (active low; byte mode) or Receive Cell Available (active high; cell mode).
Receive Reference signal (active low). This pin is driven in response to a received X_8 command byte.
Assertion duration is programmable to 1,2,4 or 8 clocks, as set via register 0x03, bits 3,4.
Receive data bit 0.
Receive data bit 1.
Receive data bit 2.
Receive data bit 3.
Receive data bit 4.
Receive data bit 5.
Receive data bit 6.
Receive data bit 7.
Parity bit for RxData[7:0].
Receive data path synchronization clock.
Receive Enable signal (active low).
Transmit Full (active low; byte mode) or Transmit Cell Available (active high; cell mode).
Transmit Start of Cell signal.
Transmit Enable signal (active low).
Transmit data path synchronization clock.
Parity bit for TxData[7:0]. If unused, this pin must be tied high or low.
Transmit data bit 7.
Transmit data bit 6.
Transmit data bit 5.
Transmit data bit 4.
Transmit data bit 3.
Transmit data bit 2.
Transmit data bit 1.
Transmit data bit 0.
Transmit Reference signal input (active low). Assertion (falling edge) of this pin stimulates insertion of com-
mand byte X_8 into the transmit data stream.
Reset signal (active low).
Interrupt signal (active low). Always driven.
Address/Data bit 7. Not used for addressing.
Address/Data bit 6. Not used for addressing.
Address/Data bit 5. Not used for addressing.
Address/Data bit 4. Not used for addressing.
Address/Data bit 3. Not used for addressing.
Address/Data bit 2.
Address/Data bit 1.
Address/Data bit 0.
Utility Bus Chip select (active low).
Table 1 Pin Description (Part 2 of 2)
5 of 24
Description
September 11, 2000