IDT77V107L25PFI IDT, Integrated Device Technology Inc, IDT77V107L25PFI Datasheet - Page 4

• Manufacturer Part Number: IDT77V107L25PFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V107L25PFI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TXPARITY
TXSOC
DA
INT
M1, M0
OSC
RCO
RPLI
RST
RXLED
RXREF
SE
TXLED
TXREF
Signal Name
AGND
AVDD
GND
VDD
IDT77V107
20
22
75
53
99, 100
79
69
48
54
51
2
76
4
3
Pin Number
77, 80, 82, 87
78, 81, 83, 86
1, 25, 26, 32,
50, 63, 91
6, 23, 43, 68,
94, 98
In
In
In
Out
In
In
Out
Out
In
Out
Out
In
Out
In
I/O
____
____
____
____
Utopia Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the interrupt
Mode Select signals. These inputs must be connected to logic low.
Reserved signal. This output should be allowed to float (unconnected).
Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be performed after
Receive LED driver. Driven low for 223 cycles of OSC, beginning with RXSOC when a good (non-null and non-errored)
Reserved signal. This input must be connected to logic low.
Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when a cell is received for transmission.
Analog ground. AGND is ground the analog portion of the ship, which sources a more constant current than the digital
Analog power supply. AVDD supplies power to the analog portion of the chip, which draws a more constant current
Utopia Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in the Interrupt
Status Registers, as enabled in the Master Control Register. No other action is taken in the event of an error. Tie high
or low if unused.
Reserved signal. This input must be connected to logic low.
status in the appropriate interrupt Status Register is read. Interrupt sources are programmable via the interrupt Mask
Registers.
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mbps; 64 MHz for 51.2 Mbps.
Recovered Clock Output. This is the bit clock from the receive section.
power up prior to normal operation of the part.
cell is received. Drives 8 mA both high and low.
Receive Reference. Active low. RXREF pulses low for a programmable number of clock cycles when an x_8 command
byte is received.
8 mA drive current both high and low
Transmit Reference. At the falling edge of TXREF, an X_8 command byte is inserted into the transmit data stream.
Typical application is WAN timing.
Signal Description
portion.
than the digital portion. 3.3 ± 0.3V
Digital Ground.
Digital power supply. 3.3 ± 0.3V.
Table 1 Signal Descriptions (Part 2 of 2)
Power Supply Signals
4 of 24
December 2004