MCZ33889DEG Freescale, MCZ33889DEG Datasheet - Page 27

• Manufacturer Part Number: MCZ33889DEG
• Manufacturer: Freescale

Specifications of MCZ33889DEG

• Number Of Transceivers: 1
• Standard Supported: CAN 2.0
• Operating Supply Voltage (max): 18V
• Operating Supply Voltage (min): 5.5V
• Package Type: SOIC W
• Supply Current: 45mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

NORMAL REQUEST MODE
device after a wake-up event from sleep or stop mode, or
after device power up. In this mode, the VDD1 regulator is
ON, V2 is off, and the reset pin is high. As soon as the device
enters the normal request mode, an internal 350 ms timer is
started. During these 350 ms, the microcontroller of the
application must address the SBC via the SPI and configure
the watchdog register (TIM1 register). This is the condition for
the SBC to leave the Normal request Mode and enter the
Normal mode, and to set the watchdog timer according to the
configuration done during the Normal Request mode.
falls below 3.0 V. This bit is set into the MCR register. It is
reset by the MCR register read.
INTERNAL CLOCK
timings (reset, watchdog, cyclic wake-up, filtering time
etc....).
RESET PIN
microcontroller. Reset causes are:
• V
• Power on reset: at device power on or at device wake-up
• Watchdog timeout: if the watchdog is not cleared, the SBC
to 5.0 V.
SOFTWARE WATCHDOG (SELECTABLE WINDOW OR
TIMEOUT WATCHDOG)
stand-by modes for monitoring the MCU. The watchdog can
be either a window or timeout. This is selectable by the SPI
(register TIM, bit WDW). Default is the window watchdog.
The period of the watchdog is selectable by the SPI from 5.0
to 350 ms (register TIM, bits WDT0 and WDT1). When the
window watchdog is selected, the closed window is the first
half of the selected period, and the open window is the
second half of the period. The watchdog can only be cleared
within the open window time. An attempt to clear the
watchdog in the closed window will generate a reset. The
Watchdog is cleared through the SPI by addressing the TIM
register.
2.
Analog Integrated Circuit Device Data
Freescale Semiconductor
This is a temporary mode automatically accessed by the
The “BATFAIL flag” is a bit which is triggered when V
This device has an internal clock used to generate all
A reset output is available in order to reset the
threshold (parameter
until V
from sleep mode, the reset is maintained low until V
within its operation range.
will pull the reset pin low for the duration of the reset
duration time
For debug purposes at 25°C, the reset pin can be shorted
The software watchdog is used in the SBC normal and
Refer to ”table for reset pin operations” operation in mode
DD1
falling out of range: if V
DD1
returns to the nominal voltage.
(
parameter: RESET-DUR).
R
ST-TH
), the reset pin is pulled low
DD1
falls below the reset
DD1
SUP
is
WAKE-UP CAPABILITIES
when it is in sleep or stop mode. When a wake-up has
occurred, the wake-up event is stored into the WUR or CAN
registers. The MCU can then access the wake-up source.
The wake-up options are selectable through the SPI while the
device is in normal or standby mode, and prior to entering low
power mode (sleep or stop mode).
WAKE-UP FROM WAKE-UP INPUTS (L0, L1) WITHOUT
CYCLIC SENSE
states, and when changes occur to wake-up the MCU (In
sleep or stop modes). The wake-up pins are able to handle
40 V DC. The internal threshold is 3.0 V typical, and these
inputs can be used as an input port expander. The wake-up
inputs state can be read through the SPI (register WUR). L0
has a lower threshold than L1 in order to allow a connection
and wake-up from a digital output such as a CAN physical
interface.
CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND
WAKE-UP INPUTS L0, L1)
wake-up input lines (L0, L1), while the external pullup or
pulldown resistor of the switches associated to the wake-up
input lines are biased with HS1 VSUP switch. The HS1 switch
is activated in sleep or stop mode from an internal timer.
Cyclic sense and forced wake-up are exclusive. If Cyclic
sense is enabled, the forced wake-up can not be enabled.
INFO FOR CYCLIC SENSE + DUAL EDGE SELECTION
conditions are use together, the initial value for Lx inputs are
sampled in two cases:
stop mode and HS1 is active.
transition, the new value is sampled as default, then when the
device is set back into low power again, it will automatically
wake up.
The user should reset the LPC bits [D3 and D0] to 0 and
set them again to the desired value prior to enter sleep or
stop mode.
FORCED WAKE-UP
predetermined time spent in sleep or stop mode. Forced
wake-up is enabled by setting bit FWU in the LPC register.
Cyclic sense and forced wake-up are exclusive. If forced
wake-up is enabled, the Cyclic sense can not be enabled.
Several wake-up capabilities are available for the device
The wake-up lines are dedicated to sense external switch
In case the Cyclic sense and Lx both level sensitive
1) When the register LPC[D3 and D0] are set and
2) At cyclic sense event, that is when device is in sleep or
The consequence is that when the device wake up by Lx
The SBC can wake-up from a state change of one of the
The
SBC
can
wake-up
FUNCTIONAL DEVICE OPERATION
automatically
OPERATIONAL MODES
after
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