KS8995XA B3 Micrel Inc, KS8995XA B3 Datasheet - Page 16

• Manufacturer Part Number: KS8995XA B3
• Manufacturer: Micrel Inc

Specifications of KS8995XA B3

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

September 2008
Notes:
1.
Pin Number
109
112
115
119
110
111
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
47
48
11
20
26
33
10
19
25
32
84
87
86
85
78
83
5
4
RESERVE/NC
PWRDN_N
Pin Name
Reserved
Reserved
SCANEN
SMRXD0
SCONF0
SCONF1
SMRXC
RST_N
RXM1
RXM2
RXM3
RXM4
RXM5
SCRS
SCOL
RXP1
RXP2
RXP3
RXP4
RXP5
SDA
SCL
Type
Ipd/O
Ipd/O
Ipd/O
I /O
Ipu
Ipu
Ipd
I/O
Ipd
Ipd
I/O
I
I
I
I
I
I
I
I
I
I
(1)
Port
All
All
All
All
1
2
3
4
5
1
2
3
4
5
Pin Function
Full-chip power down. Active low.
Reserved pin. No connect.
No connect.
No connect.
Reset the KS8995X. Active low.
Physical receive signal - (differential).
Physical receive signal - (differential).
Physical receive signal - (differential).
Physical receive signal - (differential).
Physical receive signal - (differential).
Physical receive signal + (differential).
Physical receive signal + (differential).
Physical receive signal + (differential).
Physical receive signal + (differential).
Physical receive signal + (differential).
Factory test pin.
Output clock at 81kHz in I
Switch MII collision detect.
Dual MII configuration pin.
Dual MII configuration pin.
Pin# (91, 86, 87):
000
001
010
011
100
101
110
111
Switch MII carrier sense.
Serial data input/output in I
Switch MII receive clock. PHY or MAC mode MII.
Switch MII receive bit 0; strap option: see “Register 11[1].”
16
(2)
2.
Switch MII
Disable, Otri
PHY Mode MII
MAC Mode MII
PHY Mode SNI
Disable
PHY Mode MII
MAC Mode MII
PHY Mode SNI
2
C master mode. See “Pin# 113.”
2
C master mode. See “Pin# 113.”
Otri = Output tristated.
PHY [5] MII
Disable, Otri
Disable, Otri
Disable, Otri
Disable, Otri
Disable
PHY Mode MII
PHY Mode MII
PHY Mode MII
M9999-091508