KSZ8993MLI Micrel Inc, KSZ8993MLI Datasheet - Page 57

• Manufacturer Part Number: KSZ8993MLI
• Description: 2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, 128-Ld PQFP( , I-Temp)
• Manufacturer: Micrel Inc

Specifications of KSZ8993MLI

• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Supply Voltage (min): 1.71/3.135V
• Power Dissipation: 800mW
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Supplier Unconfirmed
• Other names: 576-3350

Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Bit
7
6
5
4
3
2
1
0
Note: Bits [2:0] are used for spanning tree support (see page 33).
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Bit
7-0
Micrel, Inc.
October 2008
Ingress VLAN
filtering
Discard non
PVID packets
Force flow
control
Back pressure
enable
Transmit
enable
enable
Learning
disable
[15:8]
Name
Reserved
Receive
Name
Default tag
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
= 1, the switch will discard packets whose VID
port membership in VLAN table bits [18:16] does
not include the ingress port.
= 0, no ingress VLAN filtering.
= 1, the switch will discard packets whose VID
does not match ingress port default VID.
= 0, no packets will be discarded
= 1, will always enable flow control on the port,
regardless of AN result.
= 0, the flow control is enabled based on AN
result.
= 1, enable port’s half duplex back pressure
= 0, disable port’s half duplex back pressure.
= 1, enable packet transmission on the port
= 0, disable packet transmission on the port
= 1, enable packet reception on the port
= 0, disable packet reception on the port
= 1, disable switch address learning capability
= 0, enable switch address learning
Description
Port’s default tag, containing
7-5 : User priority bits
4 : CFI bit
3-0 : VID[11:8]
57
Default
0
0
0
Pin value during
reset:
For port 1,
P1FFC pin
For port 2,
P2FFC pin
For port 3, this
bit has no
meaning. Flow
control is
controlled by
Reg. 6, bit 5.
Pin value during
reset:
BPEN pin
1
1
0
Default
0x00
M9999-020606
KSZ8993M/ML