DJLXT360LE.A2 Cortina Systems Inc, DJLXT360LE.A2 Datasheet - Page 11

• Manufacturer Part Number: DJLXT360LE.A2
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT360LE.A2

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

LXT360 Transceiver
Datasheet: Long Form
249231, Revision 2.1
24 January 2008
Table 3
Cortina Systems
PLCC
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V ≤ Midrange ≤ 2.7 V. Midrange may also be established by letting the pin float.
11
12
13
16
14
15
17
18
8
9
Pin #
QFP
10
13
15
19
16
18
20
21
5
7
LXT360 Transceiver Signal Descriptions (Sheet 3 of 5)
®
LXT360 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
LOS/ QPD
Symbol
NLOOP
TRSTE
JASEL
TRING
TGND
RCLK
TVCC
TTIP
EC4
I/O
DO
DO
AO
DO
DI
DI
DI
-
-
1
Receive Recovered Clock. The clock recovered from the line input signal
is output on this pin. Under LOS conditions, there is a smooth transition
from the RCLK signal (derived from the recovered data) to the MCLK
signal, which appears at the RCLK pin.
Tristate.
HARDWARE MODES:
Connect TRSTE High to force all output pins to the high impedance state.
TRSTE, in conjunction with the MODE pin, selects the operating modes
listed in
HOST MODES:
Connect TRSTE High to force all output pins to the high-impedance state.
Connect this pin Low for normal operation.
HARDWARE MODES:
Jitter Attenuation Select. Selects jitter attenuation location:
Setting JASEL High activates the jitter attenuator in the receive path.
Setting JASEL Low activates the jitter attenuator in the transmit path.
Setting JASEL to Midrange
HOST MODES:
Connect Low in Host mode.
Loss of Signal Indicator. LOS goes High upon receipt of 175 consecutive
spaces and returns Low when the received signal reaches a mark density
of 12.5% (determined by receipt of 16 marks within a sliding window of 128
bits with fewer than 100 consecutive zeros). Note that the transceiver
outputs received marks on RPOS and RNEG even when LOS is High.
QRSS Pattern Detect. In QRSS mode, QPD stays High until the
transceiver detects a QRSS pattern. When a QRSS pattern is detected, the
pin goes Low. Any bit errors cause QPD to go High for half a clock cycle.
This output can be used to trigger an external error counter. Note that a
LOS condition will cause QPD to remain High. See
Transmit Tip and Ring. Differential driver output pair designed to drive a
50 - 200 Ω load. The transformer and line matching resistors should be
selected to give the desired pulse height and return loss performance. See
Section 4.0, Application Information , on page 36
Ground return for the transmit driver power supply TVCC.
+5 VDC Power Supply for the transmit drivers. TVCC must not vary from
VCC by more than ± 0.3 V.
HARDWARE MODES:
Equalization Control 4. Used along with EC3, EC2 and EC1 pins to
specify pulse equalization, line build out and equalizer gain limit settings.
See
HOST MODES:
Connect Low in Host mode.
Network Loopback Active. Goes High to indicate that Network loopback
(NLOOP) is active. NLOOP is activated by the reception of a 00001 pattern
for five seconds. NLOOP is reset by reception of a 001 pattern for five
seconds, or by activation of Remote loopback (RLOOP).
Table 10 on page 31
Table 5 on page 19
for details.
2
.
disables jitter attenuation.
Description
TM
TM
1.1 Mode Dependent Signals
.
Figure 11 on page 26
Page 11
.