82V2088BB IDT, Integrated Device Technology Inc, 82V2088BB Datasheet - Page 14

• Manufacturer Part Number: 82V2088BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2088BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
SCLKE
GNDT1
GNDT2
GNDT3
GNDT4
GNDT5
GNDT6
GNDT7
GNDT8
VDDIO
GNDIO
VDDT1
VDDT2
VDDT3
VDDT4
VDDT5
VDDT6
VDDT7
VDDT8
VDDA
Name
TRST
TMS
TCK
TDO
TDI
Output
Pullup
Pullup
Pullup
Input
Input
Input
Input
Input
Type
-
-
-
-
-
PQFP208
103, 128
104, 130
161, 162
179, 180
181, 182
199, 200
165, 166
175, 176
185, 186
195,196
99, 100
60, 201
22, 33
20, 35
61, 62
79, 80
81, 82
65, 66
75, 76
85, 86
95, 96
204
205
208
207
206
158
157
11
Pin No.
J10, J13, K4
PBGA208
A14, B14
A12, B12
R14, T14
R12, T12
G9, G10
C1, T10
H1, K1
A9, B9
C9, D9
A4, B4
R4, T4
N9, P9
R9, T9
A7, B7
C7, D7
A2, B2
R2, T2
N7, P7
R7, T7
H4, J9
A10
B10
D13
K16
B1
A6
B6
SCLKE: Serial Clock Edge Select
Signal on this pin determines the active edge of SCLK to output SDO. The active clock edge is selected
as shown below:
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resis-
tor. To ensure deterministic operation of the test logic, TMS should be held high while the signal applied
to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edges of TCK.TMS
has an internal pullup resistor.
TCK: JTAG Test Clock
This pin is the input clock for JTAG. The data on TDI and TMS is clocked into the device on the rising
edges of TCK while the data on TDO is clocked out of the device on the falling edges of TCK. When
TCK is idle at a low level, all stored-state devices contained in the test logic will retain their state indef-
initely.
TDO: JTAG Test Data Output
This output pin is in high impedance state normally and is used for reading all the serial configuration
and test data from the test logic. The data on TDO is clocked out of the device on the falling edges of
TCK.
TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pullup resistor.
The data on TDI is clocked into the device on the rising edges of TCK.
3.3V I/O Power Supply
I/O Ground
3.3V Power Supply for Transmitter Driver
Analog Ground for Transmitter Driver
3.3V Analog Core Power Supply
Power Supplies and Grounds
SCLKE
High
Low
JTAG Signals
14
Rising edge is the active edge
Falling edge is the active edge
SCLK
Description
TEMPERATURE RANGES
INDUSTRIAL