HFIXF1110CC Intel, HFIXF1110CC Datasheet - Page 83

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HFIXF1110CC

Manufacturer Part Number
HFIXF1110CC
Description
Manufacturer
Intel
Datasheet

Specifications of HFIXF1110CC

Number Of Transceivers
1
Screening Level
Commercial
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant

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5.4.4.5
5.5
5.5.1
5.5.2
Datasheet
Figure 20. Byte Write
AC Timing Characteristics
Table 43, “I
and
module interface.
LED Interface
Introduction
The IXF1110 MAC usess a serial interface consisting of three signals to provide LED data to a
serial-to-parallel logic external driver. The three signals are as follows:
The LED_DATA stream provides data for 30 separate direct drive LEDs and allows three LEDs per
MAC port. The three LED pins outlined above are detailed in
Descriptions”.
There are two modes of operation, each with its own separate LED decode mapping. Modes of
operation and LEDs are detailed in
Modes of Operation
Mode selection is accomplished by using bit 0 of the
bit is globally selected and controls the mode of operation of all ports
5.5.2.2
I
2
C_Data Line
Table 36, “I
LED CLK: This clock is provided by the IXF1110 MAC to clock the external parallel-to-serial
shift registers.
LED DATA: This serial data is provided by the IXF1110 MAC to the external parallel-to-serial
shift registers.
LED LATCH: This latch is provided by the IXF1110 MAC to latch the data on the parallel-to-
serial shift registers.
provide the two modes of operation.
(* = DON'T CARE bit for 1k)
Intel
2
C AC Timing Characteristics” on page
R
S
T
A
T
®
2
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
C Write Cycle” on page 115
M
S
B
ADDRESS
DEVICE
Order Number: 250210, Revision: 009
Intel
S
B
L
Section 5.5.2, “Modes of
W
R
T
E
W
R
I
/
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
C
A
K
*
provide the AC timing characteristics of the optical
M
S
B
ADDRESS
115,
WORD
“LED Control ($ 0x509)” on page
Table 35, “I
Operation”.
Table 23, “LED Signal
S
B
L
A
A
C
C
K
K
2
C Bus Timing” on page
Section 5.5.2.1
DATAn
and
07-Oct-2005
152. This
Section
A
C
K
115,
S
O
T
P
83

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