RC82540EP Intel, RC82540EP Datasheet
RC82540EP
Specifications of RC82540EP
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RC82540EP Summary of contents
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Gigabit Ethernet Controller Networking Silicon Product Features PCI Bus — PCI Revision 2.3 support for 32-bit wide interface at 33 MHz and 66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — CardBus Information ...
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... The Intel products referenced in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Sept 2007 1.9 Networking Silicon — 82540EP Notes Initial Release Changed document status to Intel Confidential. Section 1.0. Replaced Block Diagram Section 2.6. Added Table footnote Section 4.1, 4.2, 4.3. Replaced tables Section 5.1. Added Visual Pin Reference Section 4.4 Removed Power Supply Characteristics; added note to I/O Char- acteristics Section 5 ...
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Contents 1.0 Introduction.................................................................................... 1 1.1 Document Scope .................................................................................................. 1 1.2 Reference Documents .......................................................................................... 2 1.3 Block Diagram ...................................................................................................... 3 2.0 Product Code ................................................................................. 5 3.0 Signal Descriptions ....................................................................... 7 3.1 Signal Type Definitions ......................................................................................... 7 3.2 PCI Bus Interface.................................................................................................. 7 ...
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Networking Silicon 5.0 Package and Pinout Information ................................................27 5.1 Device Identification ...........................................................................................27 5.2 Package Information............................................................................................28 5.3 Thermal Specifications ........................................................................................29 5.4 Pinout Information ...............................................................................................30 5.5 Visual Pin Reference ...........................................................................................39 vi ...
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... LAN. With SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF implemented using the 82540EP. In addition, on chip ASF 1 ...
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... IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers (IEEE). • Intel Ethernet Controllers Timing Device Selection Guide, AP-419, Intel Corporation. • PCI Mobile Design Guide, Rev. 1.1, PCI Special Interest Group • 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide, AP-444. Intel Corporation ...
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Block Diagram Figure 1. Gigabit Ethernet Controller Block Diagram Networking Silicon — 82540EP Data Alignment Packet Buffer Interface CSR Register Access TX Data 3 ...
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... Product Code The product ordering code for the 82540EP is: RC82540EP. Networking Silicon — 82540EP 5 ...
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... Signal Descriptions Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 3.1 Signal Type Definitions The signals of the 82540EP controller are electrically defined as follows: ...
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Networking Silicon Symbol Type C/BE#[3:0] TS PAR TS FRAME# STS IRDY# STS TRDY# STS STOP# STS IDSEL# I DEVSEL# STS VIO P 8 Name and Function Bus Command and Byte Enables. Bus command and byte enable signals are ...
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Arbitration Signals Symbol Type REQ# TS GNT# I LOCK# I 3.2.3 Interrupt Signal Symbol Type INTA# TS 3.2.4 System Signals Symbol Type CLK I M66EN I RST# I I/O CLK_RUN# OD 3.2.5 Error Reporting Signals Symbol Type SERR# OD ...
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Networking Silicon 3.2.6 Power Management Signals Symbol Type LAN_ PWR_ I GOOD PME# OD AUX_PWR I 3.2.7 Impedance Compensation Signals Symbol Type ZN_COMP I/O ZP_COMP I/O 3.2.8 SMB Signals Symbol Type SMBCLK I/O SMBDATA I/O SMB_ O ALERT# ...
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Symbol Type FL_CE# O FL_SCK O FL_SI O FLSH_SO I Note: If the LAN-disable feature is used when a Flash device is present, then care must be taken by system designers not to drive the FLSH_SO pin while the Flash ...
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Networking Silicon PHY Signals 3.5 3.5.1 Crystal Signals Symbol Type XTAL1 I XTAL2 O 3.5.2 Analog Signals Symbol Type REF P MDI[0]+/- A MDI[1]+/- A MDI[2]+/- A MDI[3]+/- A 12 Name and Function Crystal One. The Crystal One ...
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Test Interface Signals Symbol Type JTAG_TCK I JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_ I TRST# TEST I CLK_VIEW O ALTCLK_125 I CLK_BYP# I HSDACP I HSDACN I PHY_TSTPT I 3.7 Power Supply Connections 3.7.1 Digital Supplies Symbol Type ...
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Networking Silicon 3.7.3 Ground and No Connects Symbol Type GND 3.7.4 Control Signals Symbol Type CTRL15 A CTRL25 A 14 Name and Function Ground. No Connect. Do not connect any circuitry to these pins. Pull-up ...
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... Voltage, Temperature, and Timing Specifications Note: The specification values listed in this section are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 4.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings ...
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Networking Silicon Table 2. Recommended Operating Conditions Symbol Parameter Analog High V AH VDD Range Core Digital V Voltage D Range Analog Low V AL VDD Range a. Sustained operation of the device at conditions exceeding these values, ...
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Table 5. Power Specifications - D3cold D3cold - wake-up enabled unplugged/no link Typ Icc Max Icc Typ Icc (mA) (mA) (mA Total Device 240 mW ...
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Networking Silicon Table 7. Power Specifications - Complete Subsystem 2 1 Subsystem 70 mA 3.3 V current Table 8. I/O Characteristics Symbol V Voltage input LOW IL V Voltage input HIGH IH ...
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AC Characteristics Table 9. AC Characteristics: 3.3 V Interfacing Symbol CLK Clock frequency in PCI mode Table 10. 25 MHz Clock Input Requirements Symbol fi_TX_CLK TX_CLK_IN frequency a. This parameter applies to an oscillator connected to the Crystal One ...
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... Networking Silicon Figure 1. AC Test Loads for General Output Pins 4.5 Timing Specifications Note: Timing specifications are subject to change. Verify with your local Intel sales office that you have the latest information before finalizing a design. 4.5.1 PCI Bus Interface 4 ...
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Figure 2. PCI Clock Timing 3.3 V Clock 0.5 Vcc 0.4 Vcc 0.3 Vcc 4.5.1.2 PCI Bus Interface Timing Table 15. PCI Bus Interface Timing Parameters Symbol CLK to signal valid delay: bussed TVAL signals CLK to signal valid delay: ...
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Networking Silicon Figure 3. PCI Bus Interface Output Timing Measurement PCI_CLK Output Delay Tri-State Output Figure 4. PCI Bus Interface Input Timing Measurement Conditions PCI_CLK Input Table 16. PCI Bus Interface Timing Measurement Conditions Symbol VTH Input measurement ...
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Figure 5. TVAL (max) Rising Edge Test Load Figure 6. TVAL (max) Falling Edge Test Load Figure 7. TVAL (min) Test Load Networking Silicon — 82540EP Pin 1/2 inch max. 25Ω Pin 1/2 inch max. 25Ω ...
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Networking Silicon Figure 8. TVAL Test Load (PCI 5 V Signaling Environment) NOTE: Note load used for maximum times. Minimum times are specified with 0 pF load. 4.5.2 Link Interface Timing Table 17. Rise and Fall ...
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EEPROM Interface Table 18. Link Interface Clock Requirements Symbol TPW EESK pulse width a. The EEPROM clock is derived from a 125 MHz internal clock. Table 19. Link Interface Clock Requirements Symbol TDOS EEDO setup time TDOH EEDO hold ...
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... This section describes the 82540EP device, manufactured in a 196-lead ball grid array measuring 15mm x 15mm. External product identification is shown in 1mm. The pin number-to-signal mapping is indicated beginning with 5.1 Device Identification Figure 10. 82540EP Device Identification Markings RC82540EP YYWW © 'ZZ Tnnnnnnnn Country 82540EP Product Name ...
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Networking Silicon 5.2 Package Information The 82540EP device is a 196-lead ball grid array (TFBGA) measuring 15 mm dimensions are detailed in Figure 11. Dimension Diagram for the 196-pin BGA 0.32 +/-0.04 Note: No changes to existing soldering ...
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Thermal Specifications The 82540EP device is specified for operation when the ambient temperature (TA) is within the ° range of - (case temperature) is calculated using the equation (θJA - ...
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Networking Silicon 5.4 Pinout Information Table 19. PCI Address, Data, and Control Signals Signal AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] Table 20. PCI Arbitration Signals Signal REQ# GNT# ...
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Table 24. Power Management Signals Signal Pin LAN_PWR_ A9 GOOD PME# A6 Table 25. Impedance Compensation Signals Signal Pin ZN_COMP H4 Table 26. SMB Signals Signal Pin SMBCLK A10 Table 27. EEPROM and Serial FLASH Interface Signals Signal Pin EESK ...
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Networking Silicon Table 31. PHY Signals Signal XTAL1 XTAL2 REF MDI[0]- Table 32. Test Interface Signals Signal JTAG_TCK JTAG_TDI Table 33. Digital Power Signals Signal DVDD (1.5V) E11 DVDD (1.5V) E12 DVDD (1.5V) G5 DVDD (1.5V) G6 DVDD ...
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Table 35. Grounds and No Connect Signals Signal Pin VSS B3 VSS B7 VSS C10 VSS C12 VSS D4 VSS D5 VSS D6 VSS D7 VSS D8 VSS D13 VSS E2 VSS E4 VSS E5 VSS E6 Table 36. Signal ...
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Networking Silicon Table 36. Signal Names in Pin Order (Sheet (Continued) Signal Name AD[26] AD[27] VSS AD[31] RST# SMB_ALERT# LINK100# LINK1000# CTRL25 PHY REF AD[21] M66EN REQ# C/BE#[3] NC AD[28] AD[29] CLK_RUN# SMBDATA VSS ACTIVITY# ...
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Table 36. Signal Names in Pin Order (Sheet (Continued) Signal Name 3.3V VSS AD[17] VSS VSS VSS VSS VSS VSS VSS 1.5V 1.5V MDI[1]+ MDI[1]- IRDY# FRAME# C/BE#[2] VSS VSS VSS VSS VSS VSS VSS VSS PHY_TSTPT ...
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Networking Silicon Table 36. Signal Names in Pin Order (Sheet (Continued) Signal Name VSS 2.5 V 1.5V VSS STOP# INTA# DEVSEL# ZN_COMP 1.5V 1.5V 1.5V 1.5V VSS VSS 1.5V HSDACN (do not connect) MDI3]+ MDI[3]- ...
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Table 36. Signal Names in Pin Order (Sheet (Continued) Signal Name 1.5V 1.5V 1.5V 1.5V 1.5V AVSS 3.3V XTAL1 AD[14] AD[15] C/BE#[1] 1.5V 1.5V VSS CLK_BYP# (do not connect) 2.5 V 1.5V 1.5V VSS JTAG_TMS JTAG_RST# JTAG_TCK ...
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Networking Silicon Table 36. Signal Names in Pin Order (Sheet (Continued) Signal Name AD[9] AD[7] AD[4] 3.3V AD[0] 3.3V FL_SCK EEDO NC VSS SDP[6] SDP[0] NC 3.3V AD[8] AD[6] AD[3] AD[2] EECS GND FLSH_SO EEDI ...
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Visual Pin Reference AD[22] AD[21] AD[18] 2 AD[23] M66EN AD[19] SERR# 3 3.3V VSS REQ# AD[20] ALT_ 4 C/BE#[3] IDSEL AD[24] CLK125 5 AD[25] AD[26] NC VSS 6 PME# AD[27] AD[28] VSS 7 ...
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