RC82573L Intel, RC82573L Datasheet - Page 11

• Manufacturer Part Number: RC82573L
• Manufacturer: Intel

Specifications of RC82573L

• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

Datasheet—82573
2.2
2.3
PCIe* Data Signals
PCIe* Miscellaneous Signals
1. This signal is used in all three devices and has the same functionality but is denoted as AUX_PRESENT in the
B
PU
PD
PE_CLKn
PE_CLKp
PE_T0n
PE_T0p
PE_R0n
PE_R0p
PE_RST#
PE_WAKE#
AUX_
PRESENT
(AUX_PWR)
CLKREQ#
(82573L only)
Name
82573E/V and AUX_PWR in the 82573L.
Signal
Signal
Input Bias
Pull Up
This signal requires a pull-up resistor.
Pull Down
This signal requires a pull-down resistor.
1
A(In)
A(0ut)
A(In)
I
OD
I
OD
Type
Type
Reset
This signal indicates whether or not the PCIe* power and clock are available.
Wake
This signal is driven to zero when it receives a wake-up packet and either the PME
enable bit of the Power Management Control/Status Register is set to 1b or the
Advanced Power Management enabled bit of the Wake Up Control Register equals
1b.
Auxiliary Power Present
AUX_PRESENT must be pulled up to 3.3V standby power if the 82573 is powered
from standby supplies. This signal must be pulled down if auxiliary power is not
used.
Clock
The Clock Request (CLKREQ#) signal is located at ball P9 of the 82573L. When it is
sampled high, this open-drain signal alerts the system that the 82573L does not
need the PCIe* differential reference clock. During normal operation, the 82573L
keeps CLKREQ# asserted (low), and the system supplies this clock to the device on
the PE_CLKp and PE_CLKn signals. The 82573L deasserts CLKREQ# (high) when it
is in an electrical idle state (L1 and L2), and the system might choose to continue
supplying the reference clock or gate it conserving platform power. The CLKREQ#
signal should be connected to the clock driver that supplies the 82573L PCIe*
clock. If other devices use the same CLKREQ# signal, a pull-up resistor should be
used to ensure that no device pulls this signal low when it is powered off.
PCIe Differential Reference Clock
The reference clock is furnished by the system and has a 300 ppm frequency
tolerance. It is used as reference clock for PCIe transmit and receive circuitry
and is used by the PCIe core PLL to generate 125 MHz and 250 MHz clocks for
the PCIe* core logic.
PCIe* Serial Data Output
These signals connect to corresponding PERn and PERp signals on a system
motherboard or a PCIe* connector. Series AC coupling capacitors are required
at the 82573 device end. The PCIe* differential outputs are clocked at 2.5 Gb/s.
PCIe Serial Data Input
These signals connect to corresponding PETn and PETp signals on a system
motherboard or a PCIe* connector. The PCIe* differential inputs are clocked at
2.5 Gb/s.
Request.
Definition
Name and Function
Name and Function
11