GD82541ER Intel, GD82541ER Datasheet - Page 18

• Manufacturer Part Number: GD82541ER
• Manufacturer: Intel

Specifications of GD82541ER

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

82541ER Gigabit Ethernet Controller
3.5.2
3.6
12
Analog Signals (10)
Test Interface Signals (6)
MDI[0]+/-
MDI[1]+/-
MDI[2]+/-
MDI[3]+/-
IEEE_TEST-
IEEE_TEST+
TEST
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
Symbol
Symbol
A
A
A
A
A
A
Type
Media Dependent Interface [0].
1000BASE-T : In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X
configuration, MDI[0]+/- corresponds to BI_DB+/-.
100BASE_TX : In MDI configuration, MDI[0]+/- is used for the transmit pair, and in
MDI-X configuration, MDI[0]+/- is used for the receive pair.
10BASE-T : In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X
configuration, MDI[0]+/- is used for the receive pair.
Media Dependent Interface [1].
1000BASE-T : In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X
configuration, MDI[1]+/- corresponds to BI_DA+/-.
100BASE_TX : In MDI configuration, MDI[1]+/- is used for the receive pair, and in
MDI-X configuration, MDI[1]+/- is used for the transit pair.
10BASE-T : In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X
configuration, MDI[1]+/- is used for the transit pair.
Media Dependent Interface [2].
1000BASE-T : In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-X
configuration, MDI[2]+/- corresponds to BI_DD+/-.
100BASE_TX : Unused.
10BASE-T : Unused.
Media Dependent Interface [3].
1000BASE-T : In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDI-X
configuration, MDI[3]+/- corresponds to BI_DD+/-.
100BASE_TX : Unused.
10BASE-T : Unused.
IEEE test pin output minus. Used to gain access to the internal PHY clock for
1000BASE-T IEEE physical layer conformance testing.
Analog test pin output plus. Used to gain access to the internal PHY clock for
1000BASE-T IEEE physical layer conformance testing.
I
I
I
O
I
I
Type
Test Enable. Enables test mode.
Normal mode: connect to VSS.
JTAG Test Access Port Clock.
JTAG Test Access Port Data In.
JTAG Test Access Port Data Out.
JTAG Test Access Port Mode Select.
JTAG Test Access Port Reset. This is an active low reset signal for JTAG.
To disable the JTAG interface, this signal should be terminated using a
100 Ω pull-down resistor to ground. It must not be left unconnected.
Name and Function
Name and Function