FW82546GB Intel, FW82546GB Datasheet

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FW82546GB

Manufacturer Part Number
FW82546GB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82546GB

Operating Supply Voltage (typ)
1.5/2.5/3.3V
Operating Supply Voltage (min)
1.43/2.38/3V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
364
Lead Free Status / RoHS Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
FW82546GB
Manufacturer:
INTEL
Quantity:
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Part Number:
FW82546GB
Manufacturer:
INTEL/英特尔
Quantity:
20 000
a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm.
82546GB Dual Port Gigabit Ethernet
Controller
Networking Silicon
Product Features
322558-002
The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Haz-
ardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the de-
vice. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.
PCI/PCI-X
MAC
PHY
— PCI-X Revision 1.0a support for
— Multi-function PCI device
— PCI Revision 2.3 support for 32-bit wide
— IEEE 802.3x compliant flow control
— Programmable host memory receive
— Wide, optimized internal data path
— Dual 64 Kbytes configurable Transmit
— Optimized descriptor fetching and write-
— Integrated PHY for 10/100/1000 Mbps
— IEEE 802.3ab Auto-Negotiation support
— IEEE 802.3ab PHY compliance and
frequencies up to 133 MHz
or 64-bit wide interface at 33 MHz and
66 MHz
support with software controllable pause
times and threshold values
buffers (256 Bytes to 16 Kbytes) and
cache line size (16 Bytes to 256 Bytes)
architecture (128 bits)
and Receive FIFO buffers
back mechanisms
full and half duplex operation
compatibility
Host Offloading
Manageability
Two complete gigabit Ethernet connections
Eight activity and link indication outputs
Lead-free
in a single device
that directly drive LEDs
Devices that are lead-free are marked with
a circled “e1” and have the product code:
NHxxxxxx.
— PHY ability to automatically detect
— Transmit and receive IP, TCP and UDP
— Transmit TCP segmentation
— IEEE 802.1q VLAN support with
— Advanced packet filtering
— Manageability features on both ports:
— Compliance with PCI Power
polarity and cable lengths and MDI
versus MDI-X cable at all speeds
checksum off-loading capabilities
VLAN tag insertion, stripping and
packet filtering for up to 4096 VLAN
tags
SMB port, ASF 1.0, ACPI, Wake on
LAN, and PXE
Management 1.1 and ACPI 2.0 register
set compliant
a
364-pin Ball Grid Array (BGA).
Datasheet
October 2009
Revision 1.9

Related parts for FW82546GB

FW82546GB Summary of contents

Page 1

... Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the de- vice. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative. 322558-002 Datasheet — ...

Page 2

... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...

Page 3

Contents 1.0 Introduction......................................................................................................................... 1 1.1 Document Scope................................................................................................... 2 1.2 Reference Documents........................................................................................... 2 1.3 Product Codes....................................................................................................... 3 2.0 Additional 82546GB Features ............................................................................................ 5 2.1 PCI ........................................................................................................................ 5 2.2 MAC ...................................................................................................................... 5 2.3 PHY ....................................................................................................................... 5 2.4 Host Offloading...................................................................................................... 6 2.5 Manageability ...

Page 4

Networking Silicon 4.2.2 Tristate Mode Using JTAG (TAP)........................................................... 20 5.0 Voltage, Temperature, and Timing Specifications ........................................................... 21 5.1 Targeted Absolute Maximum Ratings ................................................................. 21 5.2 Recommended Operating Conditions ................................................................. 21 5.3 DC Specifications ................................................................................................ 22 5.4 AC Characteristics ...

Page 5

I/O Characteristics............................................................................................... Characteristics: 3.3 V Interfacing .................................................................. MHz Clock Input Requirements...................................................................... 25 9 Link Interface Clock Requirements ..................................................................... 25 10 EEPROM Interface Clock Requirements ............................................................ Test Loads for General Output ...

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Networking Silicon Note: This page is intentionally left blank. vi Datasheet ...

Page 7

... The Intel 82546GB integrates Intel’s fourth generation gigabit MAC and PHY to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving two channels of data at rates of 1000 Mbps, 100 Mbps Mbps. In addition, it provides a 64-bit wide direct Peripheral Component Interconnect (PCI) 2 ...

Page 8

... Networking Silicon The 82546GBis packaged 364-ball grid array and footprint compatible with ® the Intel 82544GC Gigabit Ethernet Controller and 82546EB Dual Port Gigabit Ethernet Controller. Figure 1. Gigabit Ethernet Controller Block Diagram Design For Test Interface External TBI Interface ...

Page 9

... IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers (IEEE). ® • Intel Ethernet Controllers Timing Device Selection Guide, AP-419. Intel Corporation. 1.3 Product Codes The product ordering code for the 82546GB is: FW82546GB. The lead-free product ordering code for the 82546GB is: NH82546GB. Datasheet Networking Silicon — 82546GB 3 ...

Page 10

Networking Silicon Note: This page intentionally left blank. 4 Datasheet ...

Page 11

Additional 82546GB Features 2.1 PCI Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands as well as PCI-X MRD, MRB, and MWB commands 2.2 MAC Low-latency transmit and receive queues Caches packet descriptors in ...

Page 12

Networking Silicon 2.4 Host Offloading Descriptor ring management hardware for transmit and receive 16-Kbyte jumbo frame support Interrupt coalescing (multiple packets per interrupt) 2.5 Manageability On-board SMB port Preboot eXecution Environment (PXE) Flash interface support (32-bit and 64-bit) ...

Page 13

... Single port or dual port implementation on the same board with minor option changes. • Offers lowest geometry to minimize power and size while maintaining Intel quality reliability standards • Lower power requirements • Extended temperature attainable with thermal management device for more demanding systems requiring a wider temperature range. Networking Silicon — ...

Page 14

... Networking Silicon 3.0 Signal Descriptions Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 3.1 Signal Type Definitions The signals of the 82546GB controller are electrically defined as follows: ...

Page 15

PCI Address, Data and Control Signals Symbol Type AD[63:0] TS CBE[7:0]# TS PAR TS PAR64 TS FRAME# STS IRDY# STS TRDY# STS Datasheet Name and Function Address and Data. Address and data signals are multiplexed on the same PCI ...

Page 16

Networking Silicon Symbol Type STOP# STS IDSEL# I DEVSEL# STS VIO P 3.2.2 Arbitration Signals Symbol Type REQ64# TS ACK64# TS REQ# TS GNT# I LOCK# I 3.2.3 Interrupt Signals Symbol Type INTA# OD INTB Name ...

Page 17

System Signals Symbol Type CLK I M66EN I RST# I LAN_ PWR_ I GOOD 3.2.5 Error Reporting Signals Symbol Type SERR# OD PERR# STS 3.2.6 Power Management Signals Symbol Type PME# OD AUX_PWR I Datasheet Name and Function PCI ...

Page 18

Networking Silicon 3.2.7 Impedance Compensation Signals Symbol Type ZN_COMP I/O ZP_COMP I/O 3.2.8 SMB Signals Note: A pull-up resistor with a recommended value of 4.7 K should be placed along the SMB. A precise value may be calculated ...

Page 19

Flash Interface Signals Symbol Type FL_ADDR O [18:0] FL_CS# O FL_OE# O FL_WE# O FL_DATA TS [7:2] FL_DATA [1:0]/ TS LAN_DISA BLE# 3.5 Miscellaneous Signals 3.5.1 LED Signals Symbol Type LED1/ACT# O LED0/LINK# O LED2/LINK100# O LED3/LINK1000# O 3.5.2 ...

Page 20

Networking Silicon 3.6 PHY Signals 3.6.1 Crystal Signals Symbol Type XTAL1 I XTAL2 O 3.6.2 PHY Analog Signals Symbol Type REF_A P MDIA[0]+/- A MDIA[1]+/- A MDIA[2]+/- A MDIA[3]+/- A REF_B P 14 Name and Function Crystal One. ...

Page 21

Symbol Type MDIB[0]+/- A MDIB[1]+/- A MDIB[2]+/- A MDIB[3]+/- A 3.7 Serializer / Deserializer Signals Symbol Type RXA+/- I RXB +/- TXA+/- O TXB +/- SIG_ DETECT I (A and B) Datasheet Name and Function Media Dependent Interface B [0]. ...

Page 22

Networking Silicon 3.8 JTAG Test Interface Signals Symbol Type JTAG_TCK I JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_ I TRST# CLK_VIEW O TEST# I 3.9 Power Supply Connections 3.9.1 Power Support Signals Symbol Type CTRL_15 O CTRL_25A O ...

Page 23

Ground and No Connects Symbol Type GND Reserved R Datasheet Name and Function Ground. No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors should not be connected to these pins. Reserved. ...

Page 24

Networking Silicon 4.0 Test Port Functionality 4.1 XOR Testing A common board or system-level manufacturing test for proper electrical continuity between a silicon component and the board is some type of cascaded-XOR or NAND tree test. The 82546GB ...

Page 25

I/O pins with dual-mode function for XOR test: Pin Name FLSH_CE_N When XOR tree test is selected, the following pin behavior(s) occur: • Output drivers for the pins listed as tested are all placed in high-impedance (tri-state) state to ensure ...

Page 26

Networking Silicon Pins not included in XOR test tree: • JTAG (TAP) interface: TRST_N, TCK, TDO, TMS, and TDO • Test mode decode controls TEST_DM_N, EWRAP, CLK_BYP_N, CLK_VIEW, and SDP_B[7] • Each internal PHY's analog signals including PHYREF, ...

Page 27

... Voltage, Temperature, and Timing Specifications Note: The specification values listed in this section are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 5.1 Targeted Absolute Maximum Ratings Table 2. Absolute Maximum Ratings ...

Page 28

Networking Silicon Table 3. Recommended Operating Conditions Symbol Input rise/fall time (normal input) tr/tf input rise/fall time (Schmitt input) Operating temperature range TA (ambient) TJ Junction temperature a. Sustained operation of the device at conditions ...

Page 29

Table 5.b 82546GB Dual Port Ethernet Controller Only Unplugged/No Link Typ Icc (mA Total Device 450 mW Power Table 5.c 82546GB Dual Port Ethernet Controller Only D(n) Uninitialized (LAN PWR GOOD ...

Page 30

Networking Silicon Table 5.e 82546GB SerDes Design (SerDes active) Typ Icc (mA) 3.3 V 110 2.5 V 120 1.5 V 170 Total Device 900 mW Power Table 5.f Complete Subsystem (SerDes Design - Includes the 82546GB) Complete Subsystem ...

Page 31

Table 6. I/O Characteristics Symbol Output current HIGH 3mA drivers (TTL3 6mA drivers (TTL6) 12mA drivers (TTL12 Inputs with pull-down resistors TTL inputs with pull-up resistors I 3-state output leakage current ...

Page 32

Networking Silicon Table 10. EEPROM Interface Clock Requirements Symbol fSK Table 11. AC Test Loads for General Output Pins Symbol CL TDO CL APM_WAKEUP, PME#, SDP[7:6], SDP[1:0] EE_DI, EE_SK, FL_ADDR[18:0], FL_CS#, FL_OE#, CL FL_WE#, FL_DATA[7:0] CL RX_ACTIVITY, TX_ACTIVITY, ...

Page 33

Table 13. Receiver Characteristics Symbol Parameter Differential Input Voltage V ID Swing Differential Input R IN Impedance 5.6 Timing Specifications 5.6.1 PCI/PCI-X Bus Interface 5.6.1.1 PCI/PCI-X Bus Interface Clock Table 14. PCI/PCI-X Bus Interface Clock Parameters Symbol Parameter TCYC CLK ...

Page 34

Networking Silicon 5.6.1.2 PCI/PCI-X Bus Interface Timing Table 15. PCI/PCI-X Bus Interface Timing Parameters Symbol Parameter CLK to signal valid delay: TVAL bussed signals TVAL CLK to signal valid delay: (ptp) point-to-point signals TON Float to active delay ...

Page 35

Figure 5. PCI Bus Interface Output Timing Measurement PCI_CLK Output Delay Tri-State Output Figure 6. PCI Bus Interface Input Timing Measurement Conditions PCI_CLK Input Figure 7. TVAL (max) Rising Edge Test Load Datasheet V TEST output current  leakage current ...

Page 36

Networking Silicon Figure 8. TVAL (max) Falling Edge Test Load 5.6.2 Link Interface Timing 5.6.2.1 Link Interface Rise and Fall Time Table 16. Rise and Fall Times Symbol Parameter TR Clock rise time TF Clock fall time TR ...

Page 37

Figure 9. Link Interface Rise/Fall Timing 5.6.2.2 Link Interface Transmit Timing Figure 10. Transmit Interface Timing TX_CLOCK TX_DATA[9:0] Table 17. Transmit Interface Timing Symbol GTX_CLK period TPERIOD TBI mode (1000 Mbps) TSETUP Data setup to rising GTX_CLK THOLD Data hold ...

Page 38

Networking Silicon 5.6.2.3 Link Interface Receive Timing Figure 11. Receive Interface Timing RBC1 RX_DATA[9:0] COM_DET RBC0 Table 18. Receive Interface Timing Symbol RBC0/RBC1 frequency TREQ TBI mode (1000 Mbps) TSETUP Data setup before rising RBC0/RBC1 THOLD Data hold ...

Page 39

Flash Interface Figure 12. Flash Read Timing Flash Address [18:0] Table 19. Flash Read Operation Timing Symbol TCE Flash CE# or OE# to read data delay TACC Flash address setup time THOLD Data hold time Figure 13. Flash Write ...

Page 40

Networking Silicon Table 20. Flash Write Operation Timing Symbol TWE Flash write pulse width (WE#) TAH Flash address hold time TDS Flash data setup time 5.6.4 EEPROM Interface Table 21. Link Interface Clock Requirements Symbol TPW EE_SK pulse ...

Page 41

... FW82546GB (c)’ZZ YYWW Tnnnnnnnn Country NOTE: The black mark in the lower left corner indicates the location of pin 1. Datasheet Networking Silicon — 82546GB (R) FW82546GB Intel (C)'ZZ YYWW Tnnnnnnnn Country Product Name Intel Product Number Copyright Information Date Code Lot Trace Code ...

Page 42

Networking Silicon 6.2 Package Information The 82546GB device is a 364-lead ball grid array (BGA) measuring 21 mm dimensions are detailed in the figures below. The nominal ball pitch is 1 mm. Figure 15. 82546GB 364-Lead BGA Ball ...

Page 43

Figure 16. 82546GB Mechanical Specifications Datasheet Networking Silicon — 82546GB 37 ...

Page 44

... The use of a heat sink device can enhance the overall tolerance of higher overall ambient air temperatures is desired. Intel does not qualify or recommend any specific heat sink device for use with the 82546GB Gigabit Ethernet controller but can provide a thermal report modeling a generic heat sink device and the with the use of a heat sink device ...

Page 45

Ball Mapping Diagram Note: The 82546GB device uses five categories of VDD connections: VDDO (3.3 V), AVDDH (Analog 3.3 V), AVDDL (Analog 2.5 V), and DVDD (1.5 V ...

Page 46

Networking Silicon 6.5 Pinout Information Table 24. PCI Address, Data, and Control Signals Signal PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] ...

Page 47

Table 26. Interrupt Signals Signal INTA# Table 27. System Signals Signal PCICLK M66EN Table 28. Error Reporting Signals Signal SERR# Table 29. Power Management Signals Signal PME# Table 30. Impedance Compensation Signals Signal ZN_COMP Table 31. SMB Signals Signal SMBCLK ...

Page 48

Networking Silicon Table 33. Flash Interface Signals Signal FL_ADDR[0] FL_ADDR[1] FL_ADDR[2] FL_ADDR[3] FL_ADDR[4] FL_ADDR[5] FL_ADDR[6] FL_ADDR[7] FL_ADDR[8] FL_ADDR[9] Table 34. LED Signals Signal ACT_A# LINK_A# LINKA100# Table 35. Software Definable Signals Signal SDPA[0] SDPA[1] SDPA[6] SDPA[7] Table 36. ...

Page 49

Table 37. PHY Signals Signal MDIA0+ MDIA1- MDIA1+ Table 38. Serializer / Deserializer Signals Signal RXA+ RXA- RXB+ RXB- Table 39. JTAG Test Interface Signals Signal JTAG_TCK JTAG_TDI JTAG_TDO Table 40. Power Support Signals Signal CTRL_15 Datasheet Networking Silicon — ...

Page 50

Networking Silicon Table 41. Digital Power Signals Signal VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) - PHY B VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO ...

Page 51

Table 43. Grounds and No Connect Signals Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Datasheet Networking Silicon — ...

Page 52

Networking Silicon Table 44. Reserved Signals Signal Reserved[0] Reserved[1] Reserved[2] Reserved[3] Reserved[4] Reserved[5] Reserved[6] Reserved[7] Reserved[8] Reserved[9] 46 Pin Signal Pin D4 Reserved[10] E10 D5 Reserved[11 Reserved[12 Reserved[13 Reserved[14 Reserved[15] ...

Page 53

Note: This page intentionally left blank. Datasheet Networking Silicon — 82546GB 47 ...

Page 54

Networking Silicon 48 Datasheet ...

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