LU82551ER Intel, LU82551ER Datasheet - Page 41

• Manufacturer Part Number: LU82551ER
• Manufacturer: Intel

Specifications of LU82551ER

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

5.6.1
5.6.2
5.6.3
5.6.4
Datasheet
Full Duplex
When operating in full duplex mode the 82551ER can transmit and receive frames simultaneously.
Transmission starts regardless of the state of the internal receive path. Reception starts when the
internal PHY detects a valid frame on the receive differential pair of the PHY.
The 82551ER operates in either half duplex mode or full duplex mode. For proper operation, both
the 82551ER CSMA/CD module and the PHY unit must be set to the same duplex mode. The
CSMA duplex mode is set by the 82551ER Configure command or forced by the settings in the
PHY unit’s registers.
The PHY duplex mode is set either by Auto-Negotiation or, if Auto-Negotiation is disabled, by
setting the full duplex bit in the Management Data Interface (MDI) Register 0, bit 8. By default, the
internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the
duplex setting of the CSMA unit. The CSMA configuration should match the result of the Auto-
Negotiation.
The selection of duplex operation (full or half) and flow control is done in two levels: MAC and
PHY. The MAC duplex selection is done only through the CSMA configuration mechanism (in
other words, the Configure command in software).
Flow Control
The 82551ER supports IEEE 802.3x frame-based flow control frames in both full duplex and half
duplex switched environments. The 82551ER flow control feature is not intended to be used in
shared media environments.
The PHY unit’s duplex and flow control enable can be selected using the NWay* Auto-Negotiation
algorithm or through the Management Data Interface.
Address Filtering Modifications
The 82551ER can be configured to ignore one bit when checking for its Individual Address (IA) on
incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least
significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority
indication bit. When configured to do so, the 82551ER passes any frame that matches all other 47
address bits of its IA, regardless of the U/L bit value.
This configuration only affects the 82551ER specific IA and not multicast, multi-IA or broadcast
address filtering. The 82551ER does not attribute any priority to frames with this bit set, it simply
passes them to memory regardless of this bit.
VLAN Support
The 82551ER controller supports the VLAN standard as currently defined by the IEEE 802.1
committee. All VLAN receive flows will be implemented by software. The 82551ER supports the
reception of long frames, specifically frames longer than 1518 bytes, including CRC, if software
sets the Long Receive OK bit in the Configuration command. Otherwise, “long” frames are
discarded.
Networking Silicon — 82551ER
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