CPC7594MC IXYS, CPC7594MC Datasheet
CPC7594MC
Specifications of CPC7594MC
Related parts for CPC7594MC
CPC7594MC Summary of contents
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Features • TTL logic level inputs for 3.3V logic interfaces Smart logic for power up / hot plug state control • • Small 16-pin SOIC or Micro-Leadframe Package MLP package printed-circuit board footprint is 60 • percent smaller than the ...
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CPC7594 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Specifications 1.1 Package Pinout CPC7594 TEST TEST GND BAT BAT BAT LINE LINE RINGING RINGING LATCH ...
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CPC7594 1.3 Absolute Maximum Ratings Parameter Minimum Maximum +5 V power supply (V ) -0.3 DD Battery Supply - Separation -5 GND GND V Logic input voltage -0.3 Logic input to switch output - isolation Switch open-contact ...
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Switch Specifications 1.6.1 Break Switches, SW1 and SW2 Parameter Test Conditions V (differential SW1 V (differential SW2 All-Off state. +25° (differential) = -320 V to gnd SW V (differential) = +260 V to ...
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CPC7594 1.6.2 Ringing Return Switch, SW3 Parameter Test Conditions V (differential SW3 All-Off state. +25° (differential) = -320 V to gnd SW V (differential) = +260 Off-State +85° C, Leakage Current ...
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Ringing Switch, SW4 Parameter Test Conditions V (differential SW4 All-Off state. +25° (differential) = -255 V to +210 (differential) = +255 V to -210 V SW Off-State +85° C Leakage Current V ...
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CPC7594 1.6.4 Test Switches, SW5 and SW6 Parameter Test Conditions V (differential SW1 V (differential SW2 All-Off state. +25° (differential) = -320 V to gnd SW V (differential) = +260 V to -60 V ...
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Digital I/O Electrical Specifications Parameter Test Conditions Input Characteristics Input voltage, Logic low Input voltage falling Input voltage, Logic high Input voltage rising Input leakage current, IN and 5 RINGING TEST DD BAT ...
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CPC7594 1.9 Protection Circuitry Electrical Specifications Parameter Conditions Protection Diode Bridge Forward Voltage drop, Apply ± dc current limit of break continuous current switches (50/60 Hz) Forward Voltage drop, Apply ± dynamic current limit of break surge current switches Optional ...
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Truth Tables 1.10.1 CPC7594xA and CPC7594xB Truth Table IN IN State RINGING TEST Talk 0 Test 0 Ringing 1 All-Off 1 Latched X All-Off High Impedance. Because T has an internal pull up at this ...
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CPC7594 2. Functional Description 2.1 Introduction 2.1.1 CPC7594xA and CPC7594xB Logic States Talk. Break switches SW1 and SW2 closed, ringing • switches SW3 and SW4 open, and test switches SW5 and SW6 open. • Ringing. Break switches SW1 and SW2 ...
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To facilitate hot plug insertion and power up control the LATCH pin has an integrated weak pull up resistor to the V power rail that will hold a non-driven LATCH DD pin at a logic high state. This enables board ...
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CPC7594 2.3.3 Table 1: Make-Before-Break Ringing to Talk Transition Logic Sequence IN IN State LATCH RINGING TEST Ringing 1 0 Make- before break Talk 0 0 2.3.4 Break-Before-Make Operation Break-before-make operation of the CPC7594 can be achieved ...
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Pull logic low to end the ringing state. SD This opens the ringing return switch (SW3) and prevents any other switches from closing. 2. Keep T low for at least one-half the duration of SD the ...
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CPC7594 As an input, the T pin is utilized to place the SD CPC7594 into the “All-Off” state by simply pulling the input to a logic low. For applications using low-voltage logic devices (lower than V ), Clare recommends the ...
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In order for the SCR to crowbar (or foldback), the SCR’s on-voltage (see “Protection Circuitry Electrical Specifications” on page 10) must be less than the applied voltage at the V pin. If the V BAT less negative than the SCR ...
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CPC7594 3. Manufacturing Information 3.1 Mechanical Dimensions 3.1.1 SOIC 3.1.2 MLP 0.55±0.10 0.23 0.55±0.10 0.80 18 7.00 0.25 ± 6.00 0.25 INDEX AREA TOP VIEW 0.90±0.10 SIDE VIEW 0.20 0.02 +0.03, -0.02) 0.33 +0.07, -0.05 1 1.80 0.40 0.55±0.10 16 ...
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Printed-Circuit Board Layout 3.2.1 SOIC (Top View) PC Board Pattern 1.270 (0.050) 9.728 ± 0.051 (0.383 ± 0.002) 1.193 (0.047) DIMENSIONS 0.787 INCHES (0.031) (MM) 3.2.2 MLP 5.60 0.80 on center 1.10 0.45 6.65 5.45 on center Detail A ...
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CPC7594 3.3 Tape and Reel Packaging 3.3.1 SOIC 330.2 DIA. (13.00 DIA) Top Cover Tape Thickness 0.102 MAX (0.004 MAX) Embossed Carrier Embossment 3.3.2 MLP MLP tape and reel drawing specifications not available at time of document release. Please contact ...