CPC7594MB IXYS, CPC7594MB Datasheet

CPC7594MB

Manufacturer Part Number

CPC7594MB

Description

Manufacturer

IXYS

Datasheet

1.CPC7594MB.pdf (20 pages)

Specifications of CPC7594MB

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Features

•

Applications

•

Figure 1. CPC7594 Block Diagram

DS-CPC7594 - R01.1

TTL logic level inputs for 3.3V logic interfaces

Smart logic for power up / hot plug state control

Small 16-pin SOIC or Micro-Leadframe Package

MLP package printed-circuit board footprint is 60

percent smaller than the SOIC version, 70 percent

smaller than 4

Monolithic IC reliability

Low matched R

Eliminates the need for zero cross switching

Flexible switch timing to transition from ringing mode

to talk mode.

Clean, bounce-free switching

Tertiary protection consisting of integrated current

limiting, voltage clamping, and thermal shutdown for

SLIC protection

5 V operation with power consumption < 10 mW

Intelligent battery monitor

Latched logic-level inputs, no external drive circuitry

required

VoIP Gateways

Central office (CO)

Digital Loop Carrier (DLC)

PBX Systems

Digitally Added Main Line (DAML)

Hybrid Fiber Coax (HFC)

Fiber in the Loop (FITL)

Pair Gain System

Channel Banks

Ring

Tip

generation EMR solutions.

TEST

Secondary

Protection

CHANTEST

BAT

RINGING

)

LINE

300

(min.)

Ω

SW3

SW4

RINGING

SW1

SW2

RINGING

SW6

SW5

GND

www.clare.com

(CPC7594xA/C)

SCR Trip Circuit

CPC7594

Description

The CPC7594 is a member of Clare’s next generation

Line Card Access Switch family. This monolithic 6-pole

solid-state switch is available in either a 16-pin SOIC

or a 16-pin MLP package. It provides the necessary

functions to replace two 2-Form-C electro-mechanical

relays used on traditional analog and contemporary

integrated voice and data (IVD) line cards found in

Central Office, Access, and PBX equipment. Because

this device contains solid state switches for tip and ring

line break, ringing injection/return and channel test

access, it requires only a +5V supply for operation and

TTL logic-level inputs for control.

The CPC7594 is particularly designed for IVD line

cards where an EMR is required for line test due to the

high frequencies typical of ADSL but solid-state

switches are desired for switching and test-in

functions.

The CPC7594xC logic differs from the CPC7594xA/B

logic by providing a monitor function during the test

state.

Ordering Information

Specify CPC7594Bx for the SOIC package (47/tube)

or CPC7594Mx for the MLP (94/tube). Add “TR”, sans

quotes, to the part number for tape and reel

packaging. SOIC: 1000/reel or MLP: 2000/reel.

CPC7594xA

CPC7594xB

CPC7594xC

Part Number Description

REF

BAT

Control

Switch

+5V

Logic

GND

6-pole LCAS with protection SCR in tubes

6-pole LCAS without protection SCR in tubes

6-pole LCAS with protection SCR and “Monitor”

test state in tubes

Line Card Access Switch

BAT

LATCH

SLIC

TEST

RINGING

CPC7594

Related parts for CPC7594MB

CPC7594MB Summary of contents

Page 1

Features • TTL logic level inputs for 3.3V logic interfaces Smart logic for power up / hot plug state control • • Small 16-pin SOIC or Micro-Leadframe Package MLP package printed-circuit board footprint is 60 • percent smaller than the ...

Page 2

CPC7594 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

Specifications 1.1 Package Pinout CPC7594 TEST TEST GND BAT BAT BAT LINE LINE RINGING RINGING LATCH ...

Page 4

CPC7594 1.3 Absolute Maximum Ratings Parameter Minimum Maximum +5 V power supply (V ) -0.3 DD Battery Supply - Separation -5 GND GND V Logic input voltage -0.3 Logic input to switch output - isolation Switch open-contact ...

Page 5

Switch Specifications 1.6.1 Break Switches, SW1 and SW2 Parameter Test Conditions V (differential SW1 V (differential SW2 All-Off state. +25° (differential) = -320 V to gnd SW V (differential) = +260 V to ...

Page 6

CPC7594 1.6.2 Ringing Return Switch, SW3 Parameter Test Conditions V (differential SW3 All-Off state. +25° (differential) = -320 V to gnd SW V (differential) = +260 Off-State +85° C, Leakage Current ...

Page 7

Ringing Switch, SW4 Parameter Test Conditions V (differential SW4 All-Off state. +25° (differential) = -255 V to +210 (differential) = +255 V to -210 V SW Off-State +85° C Leakage Current V ...

Page 8

CPC7594 1.6.4 Test Switches, SW5 and SW6 Parameter Test Conditions V (differential SW1 V (differential SW2 All-Off state. +25° (differential) = -320 V to gnd SW V (differential) = +260 V to -60 V ...

Page 9

Digital I/O Electrical Specifications Parameter Test Conditions Input Characteristics Input voltage, Logic low Input voltage falling Input voltage, Logic high Input voltage rising Input leakage current, IN and 5 RINGING TEST DD BAT ...

Page 10

CPC7594 1.9 Protection Circuitry Electrical Specifications Parameter Conditions Protection Diode Bridge Forward Voltage drop, Apply ± dc current limit of break continuous current switches (50/60 Hz) Forward Voltage drop, Apply ± dynamic current limit of break surge current switches Optional ...

Page 11

Truth Tables 1.10.1 CPC7594xA and CPC7594xB Truth Table IN IN State RINGING TEST Talk 0 Test 0 Ringing 1 All-Off 1 Latched X All-Off High Impedance. Because T has an internal pull up at this ...

Page 12

CPC7594 2. Functional Description 2.1 Introduction 2.1.1 CPC7594xA and CPC7594xB Logic States Talk. Break switches SW1 and SW2 closed, ringing • switches SW3 and SW4 open, and test switches SW5 and SW6 open. • Ringing. Break switches SW1 and SW2 ...

Page 13

To facilitate hot plug insertion and power up control the LATCH pin has an integrated weak pull up resistor to the V power rail that will hold a non-driven LATCH DD pin at a logic high state. This enables board ...

Page 14

CPC7594 2.3.3 Table 1: Make-Before-Break Ringing to Talk Transition Logic Sequence IN IN State LATCH RINGING TEST Ringing 1 0 Make- before break Talk 0 0 2.3.4 Break-Before-Make Operation Break-before-make operation of the CPC7594 can be achieved ...

Page 15

Pull logic low to end the ringing state. SD This opens the ringing return switch (SW3) and prevents any other switches from closing. 2. Keep T low for at least one-half the duration of SD the ...

Page 16

CPC7594 As an input, the T pin is utilized to place the SD CPC7594 into the “All-Off” state by simply pulling the input to a logic low. For applications using low-voltage logic devices (lower than V ), Clare recommends the ...

Page 17

In order for the SCR to crowbar (or foldback), the SCR’s on-voltage (see “Protection Circuitry Electrical Specifications” on page 10) must be less than the applied voltage at the V pin. If the V BAT less negative than the SCR ...

Page 18

CPC7594 3. Manufacturing Information 3.1 Mechanical Dimensions 3.1.1 SOIC 3.1.2 MLP 0.55±0.10 0.23 0.55±0.10 0.80 18 7.00 0.25 ± 6.00 0.25 INDEX AREA TOP VIEW 0.90±0.10 SIDE VIEW 0.20 0.02 +0.03, -0.02) 0.33 +0.07, -0.05 1 1.80 0.40 0.55±0.10 16 ...

Page 19

Printed-Circuit Board Layout 3.2.1 SOIC (Top View) PC Board Pattern 1.270 (0.050) 9.728 ± 0.051 (0.383 ± 0.002) 1.193 (0.047) DIMENSIONS 0.787 INCHES (0.031) (MM) 3.2.2 MLP 5.60 0.80 on center 1.10 0.45 6.65 5.45 on center Detail A ...

Page 20

CPC7594 3.3 Tape and Reel Packaging 3.3.1 SOIC 330.2 DIA. (13.00 DIA) Top Cover Tape Thickness 0.102 MAX (0.004 MAX) Embossed Carrier Embossment 3.3.2 MLP MLP tape and reel drawing specifications not available at time of document release. Please contact ...

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