CT2-ML2LACW31C4 JDS UNIPHASE, CT2-ML2LACW31C4 Datasheet - Page 4
![no-image](/images/no-image-200.jpg)
CT2-ML2LACW31C4
Manufacturer Part Number
CT2-ML2LACW31C4
Description
Manufacturer
JDS UNIPHASE
Datasheet
1.CT2-ML2LACW31C4.pdf
(9 pages)
Specifications of CT2-ML2LACW31C4
Number Of Transmitters
1
Power Supply Requirement
Single
Operating Temperature Classification
Commercial
Pin Count
20
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Supply Current
350mA
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Lead Free Status / RoHS Status
Supplier Unconfirmed
4
CT2 Electrical Pad Layout
Transceiver Pin Descriptions
Pin
TD
TDb
RD
RDb
Rate_select
TxDIS
LOS
Tx_fault
MOD_DEF(0)
MOD_DEF(1)
MOD_DEF(2)
VccR,VccT
VeeR, VeeT
Description
Un-clocked, multirate, differential serial bit stream (155 Mb/s to 2.7 Gb/s) used to drive the optical transmitter.
Internally AC coupled and terminated via internal 100 Ω differential impedence.
Differential received electrical signal capable of detecting 155 Mb/s to 2.7 Gb/s bit patterns.
The differential pair is internally biased and AC coupled. This signal requires 100 Ω external differential termination.
Internally monitored and available for future use. Can be customized for specific applications.
Transmitter Disable Input. A logic HIGH on this input pin disables the transmitter's laser so that there is no optical
output. If left open the transmitter will be disabled.
Loss of Signal (Open Collector). A logic HIGH on this output indicates an incoming signal level that is less than -25 dBm
but no greater than -31 dBm for the 40 km configuration and less than -34 dBm but no greater than -40 dBm for the
80 km configuration. LOS shall deassert (logic LOW) when a 3 dB (maximum), 0.5 dB (minimum) hysteresis is obtained.
Transmitter fault (Open collector). A logic HIGH indicates that the transmitter is in a fault condition.
MOD_DEF(0) is internally grounded to indicate the presence of the module. Must be pulled-up on host board with
10 KΩ resistor.
MOD_DEF(1) is the clock of the 2 wire interface for module monitoring.
MOD_DEF(2) is the data line of the 2 wire interface for module monitoring.
Receiver, Transmitter power supply, respectively
Receiver, Transmitter ground, respectively. The chassis ground and circuit ground isolation is configurable.
20
19
18
17
16
15
14
13
12
11
Top of Board
TD-
TD+
VccT
VccR
VeeR
RD-
VeeR
VeeT
VeeT
RD+
2.5 GB/S CWDM SFP TRANSCEIVER
1
2
3
4
5
6
7
8
9
10
Bottom of Board (As Viewed
through Top of Board)
VeeT
Tx Disable
MOD-DEF(2)
MOD-DEF(1)
MOD-DEF(0)
Rate Select
LOS
VeeR
VeeR
Tx Fault