HI-8482PSI Holt Integrated Circuits, HI-8482PSI Datasheet
HI-8482PSI
Specifications of HI-8482PSI
Related parts for HI-8482PSI
HI-8482PSI Summary of contents
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... HOLT INTEGRATED CIRCUITS www.holtic.com HI-8482 ARINC 429 Dual Line Receiver (Top Views IN1A HI-8482J HI-8482JT 17 - CAP1B 16 - IN1B 20 - PIN PLASTIC 15 - OUT1A J-LEAD PLCC 14 - GND 20 - TESTB 19 - CAP1A HI-8482PSI 18 - IN1A HI-8482PST 17 - CAP1B 16 - IN1B 20 - PIN 15 - OUT1A PLASTIC 14 - GND SMALL OUTLINE 13 - N/C (SOIC OUT1B TRUTH TABLE TEST INPUTS ...
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... NOR function of OUTA and OUTB. The test inputs logically disconnect the outputs of the comparators from OUTA and OUTB and force the device outputs to one of the three valid states (Figure 5). This alleviates having to ground the ARINC inputs during test mode operation. ...
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... HI-8482 ground (GND) connection should be sturdy and isolated from large switching currents to provide a quiet ground reference. The HI-8482 can be used with HI-3182 or HI-8585 Line Drivers to provide a complete analog ARINC 429 interface solution. A simple application, which can be used in systems requiring a repeater type circuit for long transmissions or for test interfaces, is given in The Figure 3 ...
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... INPUT ARINC input terminal A of channel 2 TIMING DIAGRAMS +10V ARINC DIFFERENTIAL 0V INPUT -10V OUTA OUTB +5V TESTA 0V +5V TESTB 0V OUTA (test) OUTB (test) HI-8482 SYMBOL FUNCTION IN2B INPUT OUT1A OUTPUT OUT1B OUTPUT OUT2A OUTPUT OUT2B OUTPUT TESTA INPUT TESTB INPUT +V POWER L +Vs ...
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... Voltage - sourcing 2.8mA Voltage - sinking 100µA Voltage - sinking 2.0mA Rise time Fall time Propagation delay - low to high (ARINC) Propagation delay - high to low (ARINC) Propagation delay - low to high (TESTA/B) Propagation delay - low to high (TESTA/B) Supply current +VS current +VS current -VS current -VS current +VL current +VL current Notes: 1 ...
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... ADDITIONAL HI-8482 PIN CONFIGURATIONS (All 20-Pin Package Configurations) IN2B - 4 HI-8482U OUT2B - 5 HI-8482UT IN2A - 6 20-PIN CAP2A - 7 J-LEAD OUT2A - 8 CERQUAD - TESTA - 2 CAP2B - 3 HI-8482C HI-8482CT IN2B - 4 HI-8482CM-01 OUT2B - 5 IN2A - 6 20-PIN CERAMIC CAP2A - 7 SIDE-BRAZED OUT2A - 8 DIP + N HI-8482 18 - IN1A IN2B - CAP1B OUT2B - IN1B IN2A - OUT1A CAP2A - 7 ...
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... RANGE -40°C TO +85°C I -55°C TO +125°C T -55°C TO +125°C M PACKAGE DESCRIPTION 20 PIN CERAMIC SIDE BRAZED DIP (20C) 20 PIN CERAMIC LEADLESS CHIP CARRIER (20S) TEMPERATURE FLOW RANGE -40°C TO +85°C I -55°C TO +125°C T PACKAGE DESCRIPTION 20 PIN CERDIP (20D) ...
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... BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8482 PACKAGE DIMENSIONS .5035 ± .0075 (12.789 ± .191) .295 ± .002 (7.493 ± .051) .018 typ (.457) 0° to 8° ...
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... BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8482 PACKAGE DIMENSIONS .070 max 1.060 max (1.778 max) (26.924 max) .288 ±.005 (7.315 ±.127) ...
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... CERAMIC LEADLESS CHIP CARRIER .040 x 45° (1.016 x 45°) .020 INDEX (.508) PIN 1 .350 ±.008 (8.890 ±.203) SQ. BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 20-PIN J-LEAD CERQUAD .375 ± .008 (9.525 ± ...