CY7B952-SC Cypress Semiconductor Corp, CY7B952-SC Datasheet
CY7B952-SC
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CY7B952-SC Summary of contents
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... Transceiver PMC-Sierra PM5343STXC PM5344SPTX • 3901 North First Street • San Jose CY7B952 SOIC Top View 1 24 RCLK– 23 RCLK RSER– RSER LFI CY7B952 TCLK– TCLK TSER+ 12 TSER– 13 Path Overhead PMC-Sierra , CA 95134 • 408-943-2600 Revised April 27, 2004 [+] Feedback ...
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... When LOOP is LOW, the Transmit input data stream (TSER±) is used by the Receive PLL for clock and data recovery. Document #: 38-02018 Rev. *B and RIN– left unconnected, the entire Receive PLL will be powered down. CC and TSER– CY7B952 . Page [+] Feedback ...
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... CC V Ground. SS Description The CY7B952 Serial SONET/SDH Transceiver (SST) is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ (Non Return to Zero) or NRZI (Non Return to Zero Invert on ones) serial data stream. This device also provides a bit-rate Transmit clock, from a byte rate source through the use of a frequency multiplier PLL, and differential data buffering for the Transmit side of the system ...
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... SONET/SDH system such as a SONET/SDH switch. The SST provides the recovered clock and data to a serial to parallel converter and SONET/SDH Transport Overhead Processor such as the PMC-Sierra PM5343 STXC. The parallel data is then passed to a SONET/SDH Path Overhead Processor such as the PMC-Sierra PM5344 SPTX. CY7B952 . CC Page [+] Feedback ...
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... IN IHE(MAX) TSER/RIN IHE(MAX) REFCLK/ ILE(MIN) TSER/RIN ILE(MIN) TSER/RIN REFCLK TSER/RIN REFCLK CD TSER/RIN REFCLK CD (ECL) CD (Disable) T > 0°C /2. CC CY7B952 [ ± 10% 0°C to +70°C Min. Max. Unit 2 −0.5 0.8 V µA +0.5 +200 −10 µA +10 −50 µA +50 −500 µA 2.4 V 0.45 V − ...
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... [7] (b) ECL AC Test Load V IHE 80% 2.0V 20% 1.0V V ILE < < (d) ECL Input Test Waveform Description MODE=LOW MODE=HIGH MODE=LOW MODE=HIGH [6] [6] [ where x represents the number of ECL output pairs activated. CCT CCE CY7B952 Min. Max. Unit − 0. − 0.0 0. 7 Max. Unit = 5 ...
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... Jitter Generation of RX PLL −3 dB Gain Bandwidth of RX PLL f −3dB (Jitter Transfer Bandwidth) −3 dB Gain Bandwidth of RX PLL f −3dB (Jitter Transfer Bandwidth) Gpeak Maximum Peaking of RX PLL Switching Waveforms for the CY7B952 SONET/SDH Serial Transceiver t RPWL REFCLK TSER (RIN ) t PD TOUT (ROUT ) t ...
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... Ordering Information Speed (ns) Ordering Code 25 CY7B952-SC Package Diagram SUNI is a trademark of PMC-Sierra, Incorporated. SST is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-02018 Rev. *B Package Name Package Type S13 24-Lead (300-Mil) Molded SOIC ...
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... Document History Page Document Title: CY7B952 SST™ SONET/SDH Serial Transceiver Document Number: 38-02018 Orig. of REV. ECN. Issue Date Change ** 105981 03/28/01 *A 122206 12/28/02 *B 283371 See ECN Document #: 38-02018 Rev. *B Description of Change SZV Change from Spec. number: 38-00502 to 38-02018 RBI Add power up requirements to maximum ratings information. ...