AD9875BSTZ Analog Devices Inc, AD9875BSTZ Datasheet - Page 19

• Manufacturer Part Number: AD9875BSTZ
• Manufacturer: Analog Devices Inc

Specifications of AD9875BSTZ

• Main Category: Single Chip
• Sub-category: Converter
• Power Supply Type: Analog/Digital
• Operating Supply Voltage (typ): 3.3V
• Package Type: LQFP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 262mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

For the AD9875, the most significant nibble defaults to six bits
and the least significant nibble defaults to four bits. This can be
changed so that the least significant nibble and most significant
nibble have five bits each. This is done by setting the Rx Port
Width Five Bits bit (Register 8, Bit 1). In all cases, the nibbles
are justified toward Bit 5.
Also, the Rx path can be used in a reduced resolution mode by
setting the Rx Port Multiplexer Bypass bit (Register 8, Bit 0). In
this mode the Rx data word becomes six bits and is read in a
single cycle. The clocking modes are the same as described above,
but the level of Rx SYNC will stay low.
The Rx[5:0] pins can be put into a high impedance state by
setting the Three-State Rx Port bit (Register 8, Bit 3).
SERIAL INTERFACE FOR REGISTER CONTROL
The serial port is a three wire serial communications port consisting
of a clock (SCLK), chip select (SENABLE), and a bidirectional
data (SDATA) signal. The interface allows read/write access to
all registers that configure the AD9875 internal parameters.
Single or multiple byte transfers are supported as well as MSB
first or LSB first transfer formats.
General Operation of the Serial Interface
Serial communication over the serial interface can be from 1 to
5 bytes in length. The first byte is always the instruction byte.
The instruction byte establishes whether the communication is
going to be a read or write access, the number of data bytes to
be transferred and the address of the first register to be accessed.
The instruction byte transfer is complete immediately upon the
eighth rising edge of SCLK after SENABLE is asserted. Likewise,
the data registers change immediately upon writing to the eighth
bit of each data byte.
Instruction Byte
The instruction byte contains the following information as
shown below:
Bit I7 – R/W
This bit determines whether a read or a write data transfer will
occur after the instruction byte write. Logic high indicates read
operation; logic zero indicates a write operation.
Bits I6:I5 – N1:N0
These two bits determine the number of bytes to be transferred
during the data transfer cycle. The bit decodes are shown in the
table below:
REV. A
M
/ R
7 I
S
W
B
N
6 I
1
Table II. Instruction Byte Information
N
5 I
N1:N0
0:0
0:1
1:0
1:1
0
Table III. Decode Bits
A
4 I
4
Description
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
A
3 I
3
A
2 I
2
A
1 I
1
L
S
A
0 I
B
0
–19–
Bits I4:I0 – A4:A0
These bits determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The remaining
register addresses are generated by the AD9875.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK—Serial Clock
The serial clock pin is used to synchronize data transfers to and
from the AD9875 and to run the internal state machines. SCLK
maximum frequency is 25 MHz. All data transmitted to the
AD9875 is sampled on the rising edge of SCLK. All data read
from the AD9875 is validated on the rising edge of SCLK and is
updated on the falling edge.
SENABLE—Serial Interface Enable
The SENABLE pin is active low. It enables the serial communi-
cation to the device. SENABLE select should stay low during
the entire communication cycle. All input on the serial port is
ignored when SENABLE is inactive.
SDATA—Serial Data I/O
The signal on this line is sampled on the first eight rising edges of
SCLK after SENABLE goes active. Data is then read from or
written to the AD9875 depending on what was read.
Figures 8 and 9 show the timing relationships between the three
SPI signals.
Figure 8. Timing Diagram Register Write to AD9875/AD9876
Figure 9. Timing Diagram Register Read from AD9875/AD9876
MSB/LSB TRANSFERS
The AD9875 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
bit order is controlled by the SPI LSB First bit (Register 0, Bit 6).
The default is value is 0, MSB first. Multibyte data transfers in
MSB format can be completed by writing an instruction byte
that includes the register address of the last address to be accessed.
The AD9875 will automatically decrement the address for each
successive byte required for the multibyte communication cycle.
When the SPI LSB First bit (Register 0, Bit 6) is set high, the
serial port interprets both instruction and data bytes LSB first.
Multibyte data transfers in LSB format can be completed by
writing an instruction byte that includes the register address of
the first address to be accessed. The AD9875 will automatically
SENABLE
SENABLE
SDATA
SDATA
SCLK
SCLK
INSTRUCTION BIT 7
t
DS
t
DS
DATA BIT n
t
PWH
t
DH
t
SCLK
t
PWL
INSTRUCTION BIT 6
DATA BIT n–1
t
DV
AD9875