SI3056-D-FSR Silicon Laboratories Inc, SI3056-D-FSR Datasheet - Page 50

• Manufacturer Part Number: SI3056-D-FSR
• Description: Modem Chip Chipset 56Kbps 16-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3056-D-FSR

• Package: 16SOIC
• Main Category: Chipset
• Maximum Data Rate: 56 Kbps
• Typical Operating Supply Voltage: 3.3 V
• Power Supply Type: Analog
• Typical Supply Current: 15 mA
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V
• Lead Free Status / RoHS Status: Compliant

Si3018/19/10
Register 2. Control 2
Reset settings = 0000_0011
50
Bit
Name
Type
7
6
5
4
3
2
1
0
Bit
Reserved Returns to zero.
Reserved Returns to zero.
WDTEN
Name
INTE
INTP
HBE
RXE
RDI
INTE
R/W
D7
Interrupt Pin Enable.
0 = The AOUT/INT pin functions as an analog output for call progress monitoring purposes.
1 = The AOUT/INT pin functions as a hardware interrupt pin.
Interrupt Polarity Select.
0 = The AOUT/INT pin, when used in hardware interrupt mode, is active low.
1 = The AOUT/INT pin, when used in hardware interrupt mode, is active high.
Watchdog Timer Enable.
When set, this bit can only be cleared by a hardware reset. The watchdog timer monitors
register accesses. If no register accesses occur within a 4 second window, the DAA is put into
an on-hook state. A write of a DAA register restarts the watchdog timer counter. If the
watchdog timer times out, the OH and OHE bits are cleared, placing the DAA into an on-hook
state. Setting the OH bit or setting the OHE bit and asserting the OFHK pin places the DAA
back into an off-hook state.
0 = Watchdog timer disabled.
1 = Watchdog timer enabled.
Ring Detect Interrupt Mode.
This bit operates in conjunction with the RDTM and RDTI bits. This bit is selected if one or two
interrupts are generated for every ring burst.
0 = An interrupt is generated at the beginning of every ring burst.
1 = An interrupt is generated at the beginning and end of every ring burst. The interrupt at the
beginning of the ring burst must be serviced (by writing a 0 to the RDTI bit) before the end of
the ring burst for both interrupts to occur.
Hybrid Enable.
0 = Disconnects hybrid in transmit path.
1 = Connects hybrid in transmit path.
Receive Enable.
0 = Receive path disabled.
1 = Enables receive path.
INTP
R/W
D6
D5
WDTEN
R/W
D4
D3
Rev. 1.05
R/W
RDI
D2
Function
HBE
R/W
D1
RXE
R/W
D0