HY82563EB Intel, HY82563EB Datasheet - Page 28
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HY82563EB
Manufacturer Part Number
HY82563EB
Description
Manufacturer
Intel
Datasheet
1.HY82563EB.pdf
(52 pages)
Specifications of HY82563EB
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
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Part Number:
HY82563EB
Manufacturer:
INTEL
Quantity:
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82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
4.4.4
4.4.4.1
22
Table 21. 3.3V External Power Supply Parameters
a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range.
Internal LVR Power Sequencing
All supplies should rise monotonically. Sequencing of the supplies is controlled by the 82563EB/
82564EB.
Power up Sequencing and Tracking
During power up, the sequencing and tracking of the internally controlled supplies (1.9V and 1.2V)
is controlled by the 82563EB/82564EB. No specific motherboard requirements are necessary to
prevent electrical overstress or latch-up.
The delay is approximated by T
defined to the ramp rate of the 3.3V input to the internal voltage regulator circuit.
•
•
Overshoot Settling
The 82563EB/82564EB analog voltage (1.9V) will never exceed the 3.3V supply at any time
during the power up. This is because the 1.9V supply is generated from the 3.3V supply when
using the internal voltage regulator control logic (see
the internal LVR circuit). The 1.9V supply will track the 3.3V ramp.
The 82563EB/82564EB core voltage (1.2V) will never exceed the 3.3V at any time during the
power up. This is because the 1.2V supply is generated from the 3.3V supply when using the
internal voltage regulator control logic (see
internal LVR circuit). The 1.2V ramp is delayed internally to prevent it from exceeding the
1.9V and 3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp.
Overshoot
Ripple
Time
Title
(At that time delta voltage should be
lower than 5 mV from steady state
Maximum voltage ripple (peak to
Maximum overshoot allowed
Maximum overshoot allowed
ramp
Description
duration.
(3.3V)*0.25 < T
voltage)
peak)
a
Figure 5
delay
(1.2V) < T
and
Figure 5
Figure 6
Min
-
-
-
and
ramp
for a schematic of the
Figure 6
(3.3V)*0.75. T
Max
100
660
3
for a schematic of
ramp
Units
mV
mV
ms
is