EGLXT973QCA3V-873168 Cortina Systems Inc, EGLXT973QCA3V-873168 Datasheet - Page 25
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EGLXT973QCA3V-873168
Manufacturer Part Number
EGLXT973QCA3V-873168
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.EGLXT973QCA3V-873168.pdf
(97 pages)
Specifications of EGLXT973QCA3V-873168
Lead Free Status / RoHS Status
Compliant
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LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
3.2.1.2
3.2.1.3
3.3
3.3.1
3.3.2
3.3.3
Cortina Systems
MDI Crossover (MDIX)
The LXT973 Transceiver crossover function, which is compliant to the IEEE 802.3, clause
23 standard, connects the transmit output of the device to the far-end receiver in a link
segment. This function can be configured via Register bits 27.9:8. Please refer to
7.0, Auto-MDI/MDIX, on page
Fiber Interface
The LXT973 Transceiver fiber ports are designed to interface with common industry-
standard 3.3 V and 5 V fiber-optic transceivers. Each port incorporates a Low Voltage
PECL interface that complies with the ANSI X3.166 standard for seamless integration.
Fiber mode is selected through Register bit 16.0 by the following two methods:
MII Operation
The LXT973 Transceiver implements the Media Independent Interface (MII) as defined in
the IEEE 802.3 standard. Separate channels are provided for transmitting data from the
MAC to the LXT973 Transceiver (TXD), and for passing data received from the line (RXD)
to the MAC. Each channel has its own clock, data bus, and control signals. Nine signals
are used to pass received data to the MAC: RXD<3:0>, RXCLK, RXDV, RXER, COL and
CRS. Seven signals are used to transmit data from the MAC: TXD<3:0>, TXCLK, TXEN,
and TXER.
The LXT973 Transceiver supplies both clock signals as well as separate outputs for
carrier sense and collision. Data transmission across the MII is normally implemented in
4-bit-wide nibbles.
MII Clocks
The LXT973 Transceiver is the master clock source for data transmission and supplies
both MII clocks (RXCLK and TXCLK). It automatically sets the clock speeds to match link
conditions. When the link is operating at 100 Mbps, the clocks are set to 25 MHz. When
the link is operating at 10 Mbps, the clocks are set to 2.5 MHz. The transmit data and
control signals must always be synchronized to TXCLK by the MAC. The LXT973
Transceiver samples these signals on the rising edge of TXCLK.
Transmit Enable
The MAC must assert TXEN at the same time as the first nibble of preamble, and de-
assert TXEN after the last bit of the packet.
Receive Data Valid
The LXT973 Transceiver asserts RXDV when it receives a valid packet. Timing changes
depend on line operating speed:
®
1. Configure Register bit 16.0 = 1 on a per-port basis by driving the Hardware Control
2. Configure Register bit 16.0 = 1 on a per-port basis through the MDIO interface.
• For 100BASE-TX links, RXDV is asserted from the first nibble of preamble to the last
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
pin FIBER_TPn (on the respective port) to a logic Low value on power-up and/or
reset.
nibble of the data packet.
56. Default mode is auto-MDIX enabled.
3.3 MII Operation
Section
Page 25
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