WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 38

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Intel
5.6.2
5.6.3
38
Figure 9. Clocking for Link Down Clock Transition
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert TX_EN
after the last nibble of the packet.
Receive Data Valid
The LXT972M Transceiver asserts RX_DV when it receives a valid packet. Timing changes
depend on line operating speed:
•
•
For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble
of the data packet.
For 10BASE-T links, the entire preamble is truncated. RX_DV is asserted with the first nibble
of the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
RX_CLK
TX_CLK
Clock
Any
Clock transition time does not exceed
2X the nominal clock period:
10 Mbps = 2.5 MHz
100 Mbps = 25 MHz
Link-Down Condition/Auto-Negotiate Enabled
2.5 MHz
Clock
B3503-01
Document Number: 302875-005
Revision Date: 27-Oct-2005
Datasheet