DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 69
DJLXT971ALE.A4
Manufacturer Part Number
DJLXT971ALE.A4
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.DJLXT971ALE.A4.pdf
(96 pages)
Specifications of DJLXT971ALE.A4
Lead Free Status / RoHS Status
Not Compliant
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LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Figure 31
Table 36
Cortina Systems
100BASE-FX Transmit Timing
100BASE-FX Transmit Timing Parameters
®
TXD[3:0], TX_EN, TX_ER
TX_CLK High
TXD[3:0], TX_EN, TX_ER hold from
TX_CLK High
TX_EN sampled to CRS asserted
TX_EN sampled to CRS de-asserted
TX_EN sampled to TPFO out (Tx
latency)
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
3. The TX_ER signal is not shown in the figure.
LXT971A Single-Port 10/100 Mbps PHY Transceiver
testing.
rate. 100BASE-T bit time = 10
Parameter
TXD[3:0]
TXCLK
TX_EN
TPFO
CRS
0ns
3
setup to
-8
t5
t3
s or 10 ns.
t2
t1
Symbol
t1
t2
t3
t4
t5
Min
12
17
22
0
5
Typ
250ns
–
–
–
–
–
t4
1
Max
5.3
20
24
–
–
7.2 AC Timing Diagrams and
Units
B3451-02
BT
BT
BT
ns
ns
2
Test Conditions
Parameters
–
–
–
–
–
Page 69
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