IDT1893Y10LF IDT, Integrated Device Technology Inc, IDT1893Y10LF Datasheet - Page 56

• Manufacturer Part Number: IDT1893Y10LF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT1893Y10LF

• Lead Free Status / RoHS Status: Compliant

7.6 Functional Block: Management Interface
7.6.1 Management Register Set Summary
7.6.2 Management Frame Structure
ICS1893 Rev C 6/6/00
As part of the MAC/Repeater Interface, the ICS1893 provides a two-wire serial management interface
which complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used
to exchange control, status, and configuration information between a Station Management entity (STA) and
the physical layer device (PHY). The PHY and STA exchange this data through a pre-defined set of
management registers. The ISO/IEC standard specifies the following components of this serial
management interface:
•
•
•
In compliance with the ISO/IEC specification, the ICS1893 implementation of the serial management
interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the
exchange of data. These pins remain active in all ICS1893 MAC/Repeater Interface modes (that is, the
10/100 MII, 100M Symbol, and 10M Serial interface modes).
The ICS1893 implements a Management Register set that adheres to the ISO/IEC standard. This register
set (discussed in detail in
and Status registers and the ISO/IEC ‘ Extended’ registers as well as some ICS-specific registers.
The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the
exchange of configuration, control, and status data between a PHY, such as an ICS1893, and an STA. All
data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange data
through a pre-defined register set.
The ICS1893 complies with the ISO/IEC defined Management Frame Structure and protocol. This structure
supports both read and write operations.
Note:
Table 7-2.
PRE
SFD
OP
PHYAD
REGAD
TA
DATA
A set of registers
The frame structure
The protocol
Acronym
ICS1893 Data Sheet - Release
The Management Frame Structure starts from and returns to an IDLE condition. However, the
IDLE periods are not part of the Management Frame Structure.
Management Frame Structure Summary
Preamble (Bit 1.6)
Start of Frame
Operation Code
PHY Address (Bits 16.10:6)
Register Address
Turnaround
Data
Frame Field
(Section 7.6.1, “ Management Register Set Summary”
(Section 7.6.2, “ Management Frame Structure”
Frame Function
Chapter 8, “ Management Register Set”
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Table 7-2
56
11..11
01
10/01 (read/write)
AAAAA
RRRRR
Z0/10 (read/write)
DDD..DD
summarizes the Management Frame Structure.
Data
) includes the mandatory ‘ Basic’ Control
)
32 ones
2 bits
2 bits
5 bits
5 bits
2 bits
16 bits
)
Comment
Chapter 7 Functional Blocks
June, 2000