NLXT901PC.E2 S E001 Intel, NLXT901PC.E2 S E001 Datasheet - Page 30

• Manufacturer Part Number: NLXT901PC.E2 S E001
• Manufacturer: Intel

Specifications of NLXT901PC.E2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT901/907 — Universal 10BASE-T and AUI Transceivers
3.4.7
30
Figure 16. 150
PROGRAMMING
CONTROLLER
INTERFACE
BACK-END/
Link Test Enable
OPTIONS
10K
SYSTEM
LINE STATUS
82596
REMOTE
20 MHz
CLOCK
STATUS
2
150
Figure 16
10BASE-T network through the twisted-pair RJ-45 connector. (The AUI port is not used). With
MD0 tied High and MD1 tied Low, the LXT901 logic and framing are set to Mode 2 (compatible
with Intel 82596 controllers).
A 20 MHz system clock input at CLK1 is used in place of the crystal oscillator. (CLK0 is left
open). The L1 pin externally controls the link test function. The UTP/STP and NTH pins are both
tied Low, selecting the reduced receiver threshold and 150 termination for shielded twisted-pair
cable. The switch at LEDT/PDN manually controls the power-down mode.
1
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
10K
Shielded Twisted-Pair Only (LXT901 only)
Shielded Twisted-Pair Only Application (LXT901)
+5 V
shows the LXT901 in a typical twisted-pair only application. The DTE is connected to a
CLK
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
Left Open
LEDT/PDN
CLK0
VCC1
AUTOSEL
PAUI
NTH
MD0
STP
JAB
PLR
LEDC/
FDE
LEDL
CLK1
TXD
TEN
TCLK
RCLK
RXD
CD
COL
LBK
MD1
LI
TEST
LEDR
VCC2
RJAB
RLD
RCMPT
RCLK
GND1
TPONB
TPONA
TPOPA
TPOPB
RBIAS
GND2
TPIN
TPIP
37.5
37.5
75
75
1
12.4 k
0.1 F
75
75
È
2
1
6
3
8
1 : 2
1 : 1
16
14
11
9
Rev. Date: June 19, 2001
RJ45
Document #: 249097
6
5
4
3
2
1
Revision #: 002
Datasheet